2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk-provider.h>
25 #define BRRx_MASK(x) (0x3FF & x)
27 static struct rsnd_mod_ops adg_ops = {
32 struct clk *clk[CLKMAX];
33 struct clk *clkout[CLKOUTMAX];
34 struct clk_onecell_data onecell;
41 int rbga_rate_for_441khz; /* RBGA */
42 int rbgb_rate_for_48khz; /* RBGB */
45 #define LRCLK_ASYNC (1 << 0)
46 #define adg_mode_flags(adg) (adg->flags)
48 #define for_each_rsnd_clk(pos, adg, i) \
51 ((pos) = adg->clk[i]); \
53 #define for_each_rsnd_clkout(pos, adg, i) \
56 ((pos) = adg->clkout[i]); \
58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
60 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
67 for (i = 3; i >= 0; i--) {
69 if (0 == (div % ratio))
70 return (u32)((i << 8) | ((div / ratio) - 1));
76 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
78 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
79 int id = rsnd_mod_id(ssi_mod);
82 if (rsnd_ssi_is_pin_sharing(io)) {
97 return (0x6 + ws) << 8;
100 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
101 struct rsnd_dai_stream *io,
102 unsigned int target_rate,
103 unsigned int *target_val,
104 unsigned int *target_en)
106 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
107 struct device *dev = rsnd_priv_to_dev(priv);
108 int idx, sel, div, step;
109 unsigned int val, en;
110 unsigned int min, diff;
111 unsigned int sel_rate[] = {
112 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
113 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
114 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
115 adg->rbga_rate_for_441khz, /* 0011: RBGA */
116 adg->rbgb_rate_for_48khz, /* 0100: RBGB */
122 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
129 for (div = 2; div <= 98304; div += step) {
130 diff = abs(target_rate - sel_rate[sel] / div);
132 val = (sel << 8) | idx;
134 en = 1 << (sel + 1); /* fixme */
138 * step of 0_0000 / 0_0001 / 0_1101
141 if ((idx > 2) && (idx % 2))
152 dev_err(dev, "no Input clock\n");
161 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
162 struct rsnd_dai_stream *io,
163 unsigned int in_rate,
164 unsigned int out_rate,
165 u32 *in, u32 *out, u32 *en)
167 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
168 unsigned int target_rate;
174 /* default = SSI WS */
176 _out = rsnd_adg_ssi_ws_timing_gen2(io);
181 if (runtime->rate != in_rate) {
182 target_rate = out_rate;
184 } else if (runtime->rate != out_rate) {
185 target_rate = in_rate;
190 __rsnd_adg_get_timesel_ratio(priv, io,
202 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
203 struct rsnd_dai_stream *io)
205 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
206 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
207 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
208 int id = rsnd_mod_id(cmd_mod);
209 int shift = (id % 2) ? 16 : 0;
212 rsnd_adg_get_timesel_ratio(priv, io,
213 rsnd_src_get_in_rate(priv, io),
214 rsnd_src_get_out_rate(priv, io),
218 mask = 0xffff << shift;
220 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
225 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
226 struct rsnd_dai_stream *io,
227 unsigned int in_rate,
228 unsigned int out_rate)
230 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
231 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
232 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
235 int id = rsnd_mod_id(src_mod);
236 int shift = (id % 2) ? 16 : 0;
238 rsnd_mod_confirm_src(src_mod);
240 rsnd_adg_get_timesel_ratio(priv, io,
246 mask = 0xffff << shift;
250 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
251 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
254 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
255 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
258 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
259 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
262 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
263 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
266 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
267 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
272 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
277 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
279 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
280 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
281 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
282 int id = rsnd_mod_id(ssi_mod);
283 int shift = (id % 4) * 8;
284 u32 mask = 0xFF << shift;
286 rsnd_mod_confirm_ssi(ssi_mod);
291 * SSI 8 is not connected to ADG.
292 * it works with SSI 7
299 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
302 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
305 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
310 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
312 rsnd_adg_set_ssi_clk(ssi_mod, 0);
317 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
319 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
320 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
321 struct device *dev = rsnd_priv_to_dev(priv);
322 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
334 dev_dbg(dev, "request clock = %d\n", rate);
337 * find suitable clock from
338 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
341 for_each_rsnd_clk(clk, adg, i) {
342 if (rate == clk_get_rate(clk)) {
349 * find divided clock from BRGA/BRGB
351 if (rate == adg->rbga_rate_for_441khz) {
356 if (rate == adg->rbgb_rate_for_48khz) {
365 rsnd_adg_set_ssi_clk(ssi_mod, data);
367 if (!(adg_mode_flags(adg) & LRCLK_ASYNC)) {
368 if (0 == (rate % 8000))
372 rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, adg->ckr | ckr);
373 rsnd_mod_write(adg_mod, BRRA, adg->rbga);
374 rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
376 dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
377 rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
383 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
385 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
386 struct device *dev = rsnd_priv_to_dev(priv);
390 for_each_rsnd_clk(clk, adg, i) {
393 ret = clk_prepare_enable(clk);
395 clk_disable_unprepare(clk);
398 dev_warn(dev, "can't use clk %d\n", i);
402 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
403 struct rsnd_adg *adg)
405 struct device *dev = rsnd_priv_to_dev(priv);
407 static const char * const clk_name[] = {
415 for (i = 0; i < CLKMAX; i++) {
416 clk = devm_clk_get(dev, clk_name[i]);
417 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
420 for_each_rsnd_clk(clk, adg, i)
421 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
424 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
425 struct rsnd_adg *adg)
428 struct device *dev = rsnd_priv_to_dev(priv);
429 struct device_node *np = dev->of_node;
430 u32 ckr, rbgx, rbga, rbgb;
431 u32 rate, req_rate = 0, div;
433 unsigned long req_48kHz_rate, req_441kHz_rate;
435 const char *parent_clk_name = NULL;
436 static const char * const clkout_name[] = {
437 [CLKOUT] = "audio_clkout",
438 [CLKOUT1] = "audio_clkout1",
439 [CLKOUT2] = "audio_clkout2",
440 [CLKOUT3] = "audio_clkout3",
449 of_property_read_u32(np, "#clock-cells", &count);
452 * ADG supports BRRA/BRRB output only
453 * this means all clkout0/1/2/3 will be same rate
455 of_property_read_u32(np, "clock-frequency", &req_rate);
458 if (0 == (req_rate % 44100))
459 req_441kHz_rate = req_rate;
460 if (0 == (req_rate % 48000))
461 req_48kHz_rate = req_rate;
464 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
465 * have 44.1kHz or 48kHz base clocks for now.
467 * SSI itself can divide parent clock by 1/1 - 1/16
469 * rsnd_adg_ssi_clk_try_start()
470 * rsnd_ssi_master_clk_start()
473 rbga = 2; /* default 1/6 */
474 rbgb = 2; /* default 1/6 */
475 adg->rbga_rate_for_441khz = 0;
476 adg->rbgb_rate_for_48khz = 0;
477 for_each_rsnd_clk(clk, adg, i) {
478 rate = clk_get_rate(clk);
480 if (0 == rate) /* not used */
484 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
487 div = rate / req_441kHz_rate;
488 rbgx = rsnd_adg_calculate_rbgx(div);
489 if (BRRx_MASK(rbgx) == rbgx) {
491 adg->rbga_rate_for_441khz = rate / div;
492 ckr |= brg_table[i] << 20;
494 parent_clk_name = __clk_get_name(clk);
499 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
502 div = rate / req_48kHz_rate;
503 rbgx = rsnd_adg_calculate_rbgx(div);
504 if (BRRx_MASK(rbgx) == rbgx) {
506 adg->rbgb_rate_for_48khz = rate / div;
507 ckr |= brg_table[i] << 16;
508 if (req_48kHz_rate) {
509 parent_clk_name = __clk_get_name(clk);
517 * ADG supports BRRA/BRRB output only.
518 * this means all clkout0/1/2/3 will be * same rate
525 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
526 parent_clk_name, 0, req_rate);
528 adg->clkout[CLKOUT] = clk;
529 of_clk_add_provider(np, of_clk_src_simple_get, clk);
536 for (i = 0; i < CLKOUTMAX; i++) {
537 clk = clk_register_fixed_rate(dev, clkout_name[i],
540 adg->clkout[i] = ERR_PTR(-ENOENT);
542 adg->clkout[i] = clk;
544 adg->onecell.clks = adg->clkout;
545 adg->onecell.clk_num = CLKOUTMAX;
546 of_clk_add_provider(np, of_clk_src_onecell_get,
554 for_each_rsnd_clkout(clk, adg, i)
555 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
556 dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
560 int rsnd_adg_probe(struct rsnd_priv *priv)
562 struct rsnd_adg *adg;
563 struct device *dev = rsnd_priv_to_dev(priv);
564 struct device_node *np = dev->of_node;
567 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
569 dev_err(dev, "ADG allocate failed\n");
573 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
578 rsnd_adg_get_clkin(priv, adg);
579 rsnd_adg_get_clkout(priv, adg);
581 if (of_get_property(np, "clkout-lr-asynchronous", NULL))
582 adg->flags = LRCLK_ASYNC;
586 rsnd_adg_clk_enable(priv);
591 void rsnd_adg_remove(struct rsnd_priv *priv)
593 struct device *dev = rsnd_priv_to_dev(priv);
594 struct device_node *np = dev->of_node;
596 of_clk_del_provider(np);
598 rsnd_adg_clk_disable(priv);