2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/sh_clk.h>
20 struct clk *clk[CLKMAX];
22 int rbga_rate_for_441khz_div_6; /* RBGA */
23 int rbgb_rate_for_48khz_div_6; /* RBGB */
27 #define for_each_rsnd_clk(pos, adg, i) \
30 ((pos) = adg->clk[i]); \
32 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
35 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
37 struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
38 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
39 int id = rsnd_mod_id(mod);
42 if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
57 return (0x6 + ws) << 8;
60 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_dai *rdai,
62 struct rsnd_dai_stream *io,
65 int is_play = rsnd_dai_is_play(rdai, io);
66 int id = rsnd_mod_id(mod);
67 int shift = (id % 2) ? 16 : 0;
71 ws = rsnd_adg_ssi_ws_timing_gen2(io);
73 in = (is_play) ? timsel : ws;
74 out = (is_play) ? ws : timsel;
78 mask = 0xffff << shift;
82 rsnd_mod_bset(mod, SRCIN_TIMSEL0, mask, in);
83 rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out);
86 rsnd_mod_bset(mod, SRCIN_TIMSEL1, mask, in);
87 rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out);
90 rsnd_mod_bset(mod, SRCIN_TIMSEL2, mask, in);
91 rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out);
94 rsnd_mod_bset(mod, SRCIN_TIMSEL3, mask, in);
95 rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out);
98 rsnd_mod_bset(mod, SRCIN_TIMSEL4, mask, in);
99 rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out);
106 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
107 struct rsnd_dai *rdai,
108 struct rsnd_dai_stream *io,
109 unsigned int src_rate,
110 unsigned int dst_rate)
112 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
113 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
114 struct device *dev = rsnd_priv_to_dev(priv);
115 int idx, sel, div, step, ret;
117 unsigned int min, diff;
118 unsigned int sel_rate [] = {
119 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
120 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
121 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
122 adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */
123 adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */
129 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
136 for (div = 2; div <= 98304; div += step) {
137 diff = abs(src_rate - sel_rate[sel] / div);
139 val = (sel << 8) | idx;
141 en = 1 << (sel + 1); /* fixme */
145 * step of 0_0000 / 0_0001 / 0_1101
148 if ((idx > 2) && (idx % 2))
159 dev_err(dev, "no Input clock\n");
163 ret = rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
165 dev_err(dev, "timsel error\n");
169 rsnd_mod_bset(mod, DIV_EN, en, en);
174 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
175 struct rsnd_dai *rdai,
176 struct rsnd_dai_stream *io)
178 u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
180 return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
183 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
184 struct rsnd_mod *mod,
185 unsigned int src_rate,
186 unsigned int dst_rate)
188 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
189 struct device *dev = rsnd_priv_to_dev(priv);
190 int idx, sel, div, shift;
192 int id = rsnd_mod_id(mod);
193 unsigned int sel_rate [] = {
194 clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */
195 clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */
196 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */
197 0, /* 011: MLBCLK (not used) */
198 adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
199 adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */
202 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
203 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
204 for (div = 128, idx = 0;
207 if (src_rate == sel_rate[sel] / div) {
208 val = (idx << 4) | sel;
213 dev_err(dev, "can't find convert src clk\n");
217 shift = (id % 4) * 8;
218 mask = 0xFF << shift;
221 dev_dbg(dev, "adg convert src clk = %02x\n", val);
225 rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
228 rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
231 rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
236 * Gen1 doesn't need dst_rate settings,
237 * since it uses SSI WS pin.
238 * see also rsnd_src_set_route_if_gen1()
244 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
246 int id = rsnd_mod_id(mod);
247 int shift = (id % 4) * 8;
248 u32 mask = 0xFF << shift;
253 * SSI 8 is not connected to ADG.
254 * it works with SSI 7
261 rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
264 rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
267 rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
272 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
275 * "mod" = "ssi" here.
276 * we can get "ssi id" from mod
278 rsnd_adg_set_ssi_clk(mod, 0);
283 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
285 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
286 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
287 struct device *dev = rsnd_priv_to_dev(priv);
298 dev_dbg(dev, "request clock = %d\n", rate);
301 * find suitable clock from
302 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
305 for_each_rsnd_clk(clk, adg, i) {
306 if (rate == clk_get_rate(clk)) {
313 * find 1/6 clock from BRGA/BRGB
315 if (rate == adg->rbga_rate_for_441khz_div_6) {
320 if (rate == adg->rbgb_rate_for_48khz_div_6) {
329 /* see rsnd_adg_ssi_clk_init() */
330 rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
331 rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */
332 rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */
335 * This "mod" = "ssi" here.
336 * we can get "ssi id" from mod
338 rsnd_adg_set_ssi_clk(mod, data);
340 dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
341 rsnd_mod_id(mod), i, rate);
346 static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
360 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
361 * have 44.1kHz or 48kHz base clocks for now.
363 * SSI itself can divide parent clock by 1/1 - 1/16
364 * So, BRGA outputs 44.1kHz base parent clock 1/32,
365 * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
367 * rsnd_adg_ssi_clk_try_start()
370 adg->rbga_rate_for_441khz_div_6 = 0;
371 adg->rbgb_rate_for_48khz_div_6 = 0;
372 for_each_rsnd_clk(clk, adg, i) {
373 rate = clk_get_rate(clk);
375 if (0 == rate) /* not used */
379 if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
380 adg->rbga_rate_for_441khz_div_6 = rate / 6;
381 ckr |= brg_table[i] << 20;
385 if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
386 adg->rbgb_rate_for_48khz_div_6 = rate / 6;
387 ckr |= brg_table[i] << 16;
394 int rsnd_adg_probe(struct platform_device *pdev,
395 const struct rsnd_of_data *of_data,
396 struct rsnd_priv *priv)
398 struct rsnd_adg *adg;
399 struct device *dev = rsnd_priv_to_dev(priv);
400 struct clk *clk, *clk_orig;
402 bool use_old_style = false;
404 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
406 dev_err(dev, "ADG allocate failed\n");
410 clk_orig = devm_clk_get(dev, NULL);
411 adg->clk[CLKA] = devm_clk_get(dev, "clk_a");
412 adg->clk[CLKB] = devm_clk_get(dev, "clk_b");
413 adg->clk[CLKC] = devm_clk_get(dev, "clk_c");
414 adg->clk[CLKI] = devm_clk_get(dev, "clk_i");
417 * It request device dependent audio clock.
418 * But above all clks will indicate rsnd module clock
419 * if platform doesn't it
421 for_each_rsnd_clk(clk, adg, i) {
422 if (clk_orig == clk) {
424 "doesn't have device dependent clock, use independent clock\n");
425 use_old_style = true;
432 * these exist in order to keep compatible with
433 * platform which has device independent audio clock,
434 * but will be removed soon
437 adg->clk[CLKA] = devm_clk_get(NULL, "audio_clk_a");
438 adg->clk[CLKB] = devm_clk_get(NULL, "audio_clk_b");
439 adg->clk[CLKC] = devm_clk_get(NULL, "audio_clk_c");
440 adg->clk[CLKI] = devm_clk_get(NULL, "audio_clk_internal");
443 for_each_rsnd_clk(clk, adg, i) {
445 dev_err(dev, "Audio clock failed\n");
450 rsnd_adg_ssi_clk_init(priv, adg);
454 dev_dbg(dev, "adg probed\n");