sound/soc/sh/rcar/adg.c

   1 /*
   2  * Helper routines for R-Car sound ADG.
   3  *
   4  *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/clk-provider.h>
  11 #include "rsnd.h"
  12
  13 #define CLKA    0
  14 #define CLKB    1
  15 #define CLKC    2
  16 #define CLKI    3
  17 #define CLKMAX  4
  18
  19 #define CLKOUT  0
  20 #define CLKOUT1 1
  21 #define CLKOUT2 2
  22 #define CLKOUT3 3
  23 #define CLKOUTMAX 4
  24
  25 #define BRRx_MASK(x) (0x3FF & x)
  26
  27 static struct rsnd_mod_ops adg_ops = {
  28         .name = "adg",
  29 };
  30
  31 struct rsnd_adg {
  32         struct clk *clk[CLKMAX];
  33         struct clk *clkout[CLKOUTMAX];
  34         struct clk_onecell_data onecell;
  35         struct rsnd_mod mod;
  36         u32 flags;
  37         u32 ckr;
  38         u32 rbga;
  39         u32 rbgb;
  40
  41         int rbga_rate_for_441khz; /* RBGA */
  42         int rbgb_rate_for_48khz;  /* RBGB */
  43 };
  44
  45 #define LRCLK_ASYNC     (1 << 0)
  46 #define AUDIO_OUT_48    (1 << 1)
  47 #define adg_mode_flags(adg)     (adg->flags)
  48
  49 #define for_each_rsnd_clk(pos, adg, i)          \
  50         for (i = 0;                             \
  51              (i < CLKMAX) &&                    \
  52              ((pos) = adg->clk[i]);             \
  53              i++)
  54 #define for_each_rsnd_clkout(pos, adg, i)       \
  55         for (i = 0;                             \
  56              (i < CLKOUTMAX) &&                 \
  57              ((pos) = adg->clkout[i]);  \
  58              i++)
  59 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  60
  61 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  62 {
  63         int i, ratio;
  64
  65         if (!div)
  66                 return 0;
  67
  68         for (i = 3; i >= 0; i--) {
  69                 ratio = 2 << (i * 2);
  70                 if (0 == (div % ratio))
  71                         return (u32)((i << 8) | ((div / ratio) - 1));
  72         }
  73
  74         return ~0;
  75 }
  76
  77 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  78 {
  79         struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
  80         int id = rsnd_mod_id(ssi_mod);
  81         int ws = id;
  82
  83         if (rsnd_ssi_is_pin_sharing(io)) {
  84                 switch (id) {
  85                 case 1:
  86                 case 2:
  87                         ws = 0;
  88                         break;
  89                 case 4:
  90                         ws = 3;
  91                         break;
  92                 case 8:
  93                         ws = 7;
  94                         break;
  95                 }
  96         }
  97
  98         return (0x6 + ws) << 8;
  99 }
 100
 101 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 102                                        struct rsnd_dai_stream *io,
 103                                        unsigned int target_rate,
 104                                        unsigned int *target_val,
 105                                        unsigned int *target_en)
 106 {
 107         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 108         struct device *dev = rsnd_priv_to_dev(priv);
 109         int idx, sel, div, step;
 110         unsigned int val, en;
 111         unsigned int min, diff;
 112         unsigned int sel_rate[] = {
 113                 clk_get_rate(adg->clk[CLKA]),   /* 0000: CLKA */
 114                 clk_get_rate(adg->clk[CLKB]),   /* 0001: CLKB */
 115                 clk_get_rate(adg->clk[CLKC]),   /* 0010: CLKC */
 116                 adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 117                 adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 118         };
 119
 120         min = ~0;
 121         val = 0;
 122         en = 0;
 123         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 124                 idx = 0;
 125                 step = 2;
 126
 127                 if (!sel_rate[sel])
 128                         continue;
 129
 130                 for (div = 2; div <= 98304; div += step) {
 131                         diff = abs(target_rate - sel_rate[sel] / div);
 132                         if (min > diff) {
 133                                 val = (sel << 8) | idx;
 134                                 min = diff;
 135                                 en = 1 << (sel + 1); /* fixme */
 136                         }
 137
 138                         /*
 139                          * step of 0_0000 / 0_0001 / 0_1101
 140                          * are out of order
 141                          */
 142                         if ((idx > 2) && (idx % 2))
 143                                 step *= 2;
 144                         if (idx == 0x1c) {
 145                                 div += step;
 146                                 step *= 2;
 147                         }
 148                         idx++;
 149                 }
 150         }
 151
 152         if (min == ~0) {
 153                 dev_err(dev, "no Input clock\n");
 154                 return;
 155         }
 156
 157         *target_val = val;
 158         if (target_en)
 159                 *target_en = en;
 160 }
 161
 162 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 163                                        struct rsnd_dai_stream *io,
 164                                        unsigned int in_rate,
 165                                        unsigned int out_rate,
 166                                        u32 *in, u32 *out, u32 *en)
 167 {
 168         struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
 169         unsigned int target_rate;
 170         u32 *target_val;
 171         u32 _in;
 172         u32 _out;
 173         u32 _en;
 174
 175         /* default = SSI WS */
 176         _in =
 177         _out = rsnd_adg_ssi_ws_timing_gen2(io);
 178
 179         target_rate = 0;
 180         target_val = NULL;
 181         _en = 0;
 182         if (runtime->rate != in_rate) {
 183                 target_rate = out_rate;
 184                 target_val  = &_out;
 185         } else if (runtime->rate != out_rate) {
 186                 target_rate = in_rate;
 187                 target_val  = &_in;
 188         }
 189
 190         if (target_rate)
 191                 __rsnd_adg_get_timesel_ratio(priv, io,
 192                                              target_rate,
 193                                              target_val, &_en);
 194
 195         if (in)
 196                 *in = _in;
 197         if (out)
 198                 *out = _out;
 199         if (en)
 200                 *en = _en;
 201 }
 202
 203 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
 204                                  struct rsnd_dai_stream *io)
 205 {
 206         struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
 207         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 208         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 209         int id = rsnd_mod_id(cmd_mod);
 210         int shift = (id % 2) ? 16 : 0;
 211         u32 mask, val;
 212
 213         rsnd_adg_get_timesel_ratio(priv, io,
 214                                    rsnd_src_get_in_rate(priv, io),
 215                                    rsnd_src_get_out_rate(priv, io),
 216                                    NULL, &val, NULL);
 217
 218         val  = val      << shift;
 219         mask = 0xffff   << shift;
 220
 221         rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 222
 223         return 0;
 224 }
 225
 226 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
 227                                   struct rsnd_dai_stream *io,
 228                                   unsigned int in_rate,
 229                                   unsigned int out_rate)
 230 {
 231         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 232         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 233         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 234         u32 in, out;
 235         u32 mask, en;
 236         int id = rsnd_mod_id(src_mod);
 237         int shift = (id % 2) ? 16 : 0;
 238
 239         rsnd_mod_confirm_src(src_mod);
 240
 241         rsnd_adg_get_timesel_ratio(priv, io,
 242                                    in_rate, out_rate,
 243                                    &in, &out, &en);
 244
 245         in   = in       << shift;
 246         out  = out      << shift;
 247         mask = 0xffff   << shift;
 248
 249         switch (id / 2) {
 250         case 0:
 251                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0,  mask, in);
 252                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
 253                 break;
 254         case 1:
 255                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1,  mask, in);
 256                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
 257                 break;
 258         case 2:
 259                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2,  mask, in);
 260                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
 261                 break;
 262         case 3:
 263                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3,  mask, in);
 264                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
 265                 break;
 266         case 4:
 267                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4,  mask, in);
 268                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
 269                 break;
 270         }
 271
 272         if (en)
 273                 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 274
 275         return 0;
 276 }
 277
 278 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 279 {
 280         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 281         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 282         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 283         int id = rsnd_mod_id(ssi_mod);
 284         int shift = (id % 4) * 8;
 285         u32 mask = 0xFF << shift;
 286
 287         rsnd_mod_confirm_ssi(ssi_mod);
 288
 289         val = val << shift;
 290
 291         /*
 292          * SSI 8 is not connected to ADG.
 293          * it works with SSI 7
 294          */
 295         if (id == 8)
 296                 return;
 297
 298         switch (id / 4) {
 299         case 0:
 300                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
 301                 break;
 302         case 1:
 303                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
 304                 break;
 305         case 2:
 306                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
 307                 break;
 308         }
 309 }
 310
 311 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
 312 {
 313         rsnd_adg_set_ssi_clk(ssi_mod, 0);
 314
 315         return 0;
 316 }
 317
 318 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
 319 {
 320         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 321         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 322         struct device *dev = rsnd_priv_to_dev(priv);
 323         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 324         struct clk *clk;
 325         int i;
 326         u32 data;
 327         u32 ckr = 0;
 328         int sel_table[] = {
 329                 [CLKA] = 0x1,
 330                 [CLKB] = 0x2,
 331                 [CLKC] = 0x3,
 332                 [CLKI] = 0x0,
 333         };
 334
 335         dev_dbg(dev, "request clock = %d\n", rate);
 336
 337         /*
 338          * find suitable clock from
 339          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 340          */
 341         data = 0;
 342         for_each_rsnd_clk(clk, adg, i) {
 343                 if (rate == clk_get_rate(clk)) {
 344                         data = sel_table[i];
 345                         goto found_clock;
 346                 }
 347         }
 348
 349         /*
 350          * find divided clock from BRGA/BRGB
 351          */
 352         if (rate  == adg->rbga_rate_for_441khz) {
 353                 data = 0x10;
 354                 goto found_clock;
 355         }
 356
 357         if (rate == adg->rbgb_rate_for_48khz) {
 358                 data = 0x20;
 359                 goto found_clock;
 360         }
 361
 362         return -EIO;
 363
 364 found_clock:
 365
 366         rsnd_adg_set_ssi_clk(ssi_mod, data);
 367
 368         if (adg_mode_flags(adg) & LRCLK_ASYNC) {
 369                 if (adg_mode_flags(adg) & AUDIO_OUT_48)
 370                         ckr = 0x80000000;
 371         } else {
 372                 if (0 == (rate % 8000))
 373                         ckr = 0x80000000;
 374         }
 375
 376         rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, adg->ckr | ckr);
 377         rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
 378         rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
 379
 380         dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
 381                 rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
 382                 data, rate);
 383
 384         return 0;
 385 }
 386
 387 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
 388 {
 389         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 390         struct device *dev = rsnd_priv_to_dev(priv);
 391         struct clk *clk;
 392         int i, ret;
 393
 394         for_each_rsnd_clk(clk, adg, i) {
 395                 ret = 0;
 396                 if (enable)
 397                         ret = clk_prepare_enable(clk);
 398                 else
 399                         clk_disable_unprepare(clk);
 400
 401                 if (ret < 0)
 402                         dev_warn(dev, "can't use clk %d\n", i);
 403         }
 404 }
 405
 406 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 407                                struct rsnd_adg *adg)
 408 {
 409         struct device *dev = rsnd_priv_to_dev(priv);
 410         struct clk *clk;
 411         static const char * const clk_name[] = {
 412                 [CLKA]  = "clk_a",
 413                 [CLKB]  = "clk_b",
 414                 [CLKC]  = "clk_c",
 415                 [CLKI]  = "clk_i",
 416         };
 417         int i;
 418
 419         for (i = 0; i < CLKMAX; i++) {
 420                 clk = devm_clk_get(dev, clk_name[i]);
 421                 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 422         }
 423
 424         for_each_rsnd_clk(clk, adg, i)
 425                 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 426 }
 427
 428 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 429                                 struct rsnd_adg *adg)
 430 {
 431         struct clk *clk;
 432         struct device *dev = rsnd_priv_to_dev(priv);
 433         struct device_node *np = dev->of_node;
 434         struct property *prop;
 435         u32 ckr, rbgx, rbga, rbgb;
 436         u32 rate, div;
 437 #define REQ_SIZE 2
 438         u32 req_rate[REQ_SIZE] = {};
 439         uint32_t count = 0;
 440         unsigned long req_48kHz_rate, req_441kHz_rate;
 441         int i, req_size;
 442         const char *parent_clk_name = NULL;
 443         static const char * const clkout_name[] = {
 444                 [CLKOUT]  = "audio_clkout",
 445                 [CLKOUT1] = "audio_clkout1",
 446                 [CLKOUT2] = "audio_clkout2",
 447                 [CLKOUT3] = "audio_clkout3",
 448         };
 449         int brg_table[] = {
 450                 [CLKA] = 0x0,
 451                 [CLKB] = 0x1,
 452                 [CLKC] = 0x4,
 453                 [CLKI] = 0x2,
 454         };
 455
 456         ckr = 0;
 457         rbga = 2; /* default 1/6 */
 458         rbgb = 2; /* default 1/6 */
 459
 460         /*
 461          * ADG supports BRRA/BRRB output only
 462          * this means all clkout0/1/2/3 will be same rate
 463          */
 464         prop = of_find_property(np, "clock-frequency", NULL);
 465         if (!prop)
 466                 goto rsnd_adg_get_clkout_end;
 467
 468         req_size = prop->length / sizeof(u32);
 469
 470         of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
 471         req_48kHz_rate = 0;
 472         req_441kHz_rate = 0;
 473         for (i = 0; i < req_size; i++) {
 474                 if (0 == (req_rate[i] % 44100))
 475                         req_441kHz_rate = req_rate[i];
 476                 if (0 == (req_rate[i] % 48000))
 477                         req_48kHz_rate = req_rate[i];
 478         }
 479
 480         if (req_rate[0] % 48000 == 0)
 481                 adg->flags = AUDIO_OUT_48;
 482
 483         /*
 484          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 485          * have 44.1kHz or 48kHz base clocks for now.
 486          *
 487          * SSI itself can divide parent clock by 1/1 - 1/16
 488          * see
 489          *      rsnd_adg_ssi_clk_try_start()
 490          *      rsnd_ssi_master_clk_start()
 491          */
 492         adg->rbga_rate_for_441khz       = 0;
 493         adg->rbgb_rate_for_48khz        = 0;
 494         for_each_rsnd_clk(clk, adg, i) {
 495                 rate = clk_get_rate(clk);
 496
 497                 if (0 == rate) /* not used */
 498                         continue;
 499
 500                 /* RBGA */
 501                 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 502                         div = 6;
 503                         if (req_441kHz_rate)
 504                                 div = rate / req_441kHz_rate;
 505                         rbgx = rsnd_adg_calculate_rbgx(div);
 506                         if (BRRx_MASK(rbgx) == rbgx) {
 507                                 rbga = rbgx;
 508                                 adg->rbga_rate_for_441khz = rate / div;
 509                                 ckr |= brg_table[i] << 20;
 510                                 if (req_441kHz_rate &&
 511                                     !(adg_mode_flags(adg) & AUDIO_OUT_48))
 512                                         parent_clk_name = __clk_get_name(clk);
 513                         }
 514                 }
 515
 516                 /* RBGB */
 517                 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 518                         div = 6;
 519                         if (req_48kHz_rate)
 520                                 div = rate / req_48kHz_rate;
 521                         rbgx = rsnd_adg_calculate_rbgx(div);
 522                         if (BRRx_MASK(rbgx) == rbgx) {
 523                                 rbgb = rbgx;
 524                                 adg->rbgb_rate_for_48khz = rate / div;
 525                                 ckr |= brg_table[i] << 16;
 526                                 if (req_48kHz_rate &&
 527                                     (adg_mode_flags(adg) & AUDIO_OUT_48))
 528                                         parent_clk_name = __clk_get_name(clk);
 529                         }
 530                 }
 531         }
 532
 533         /*
 534          * ADG supports BRRA/BRRB output only.
 535          * this means all clkout0/1/2/3 will be * same rate
 536          */
 537
 538         of_property_read_u32(np, "#clock-cells", &count);
 539         /*
 540          * for clkout
 541          */
 542         if (!count) {
 543                 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 544                                               parent_clk_name, 0, req_rate[0]);
 545                 if (!IS_ERR(clk)) {
 546                         adg->clkout[CLKOUT] = clk;
 547                         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 548                 }
 549         }
 550         /*
 551          * for clkout0/1/2/3
 552          */
 553         else {
 554                 for (i = 0; i < CLKOUTMAX; i++) {
 555                         clk = clk_register_fixed_rate(dev, clkout_name[i],
 556                                                       parent_clk_name, 0,
 557                                                       req_rate[0]);
 558                         adg->clkout[i] = ERR_PTR(-ENOENT);
 559                         if (!IS_ERR(clk))
 560                                 adg->clkout[i] = clk;
 561                 }
 562                 adg->onecell.clks       = adg->clkout;
 563                 adg->onecell.clk_num    = CLKOUTMAX;
 564                 of_clk_add_provider(np, of_clk_src_onecell_get,
 565                                     &adg->onecell);
 566         }
 567
 568 rsnd_adg_get_clkout_end:
 569         adg->ckr = ckr;
 570         adg->rbga = rbga;
 571         adg->rbgb = rbgb;
 572
 573         for_each_rsnd_clkout(clk, adg, i)
 574                 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 575         dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 576                 ckr, rbga, rbgb);
 577 }
 578
 579 int rsnd_adg_probe(struct rsnd_priv *priv)
 580 {
 581         struct rsnd_adg *adg;
 582         struct device *dev = rsnd_priv_to_dev(priv);
 583         struct device_node *np = dev->of_node;
 584         int ret;
 585
 586         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 587         if (!adg) {
 588                 dev_err(dev, "ADG allocate failed\n");
 589                 return -ENOMEM;
 590         }
 591
 592         ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
 593                       NULL, NULL, 0, 0);
 594         if (ret)
 595                 return ret;
 596
 597         rsnd_adg_get_clkin(priv, adg);
 598         rsnd_adg_get_clkout(priv, adg);
 599
 600         if (of_get_property(np, "clkout-lr-asynchronous", NULL))
 601                 adg->flags = LRCLK_ASYNC;
 602
 603         priv->adg = adg;
 604
 605         rsnd_adg_clk_enable(priv);
 606
 607         return 0;
 608 }
 609
 610 void rsnd_adg_remove(struct rsnd_priv *priv)
 611 {
 612         struct device *dev = rsnd_priv_to_dev(priv);
 613         struct device_node *np = dev->of_node;
 614
 615         of_clk_del_provider(np);
 616
 617         rsnd_adg_clk_disable(priv);
 618 }