2 * Copyright (C) ST-Ericsson SA 2012
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
6 * Sandeep Kaushik <sandeep.kaushik@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
23 #include <mach/hardware.h>
26 #include <sound/soc.h>
28 #include "ux500_msp_i2s.h"
30 /* MSP1/3 Tx/Rx usage protection */
31 static DEFINE_SPINLOCK(msp_rxtx_lock);
33 /* Protocol desciptors */
34 static const struct msp_protdesc prot_descs[] = {
38 MSP_PHASE2_START_MODE_IMEDIATE,
39 MSP_PHASE2_START_MODE_IMEDIATE,
58 MSP_COMPRESS_MODE_LINEAR,
59 MSP_EXPAND_MODE_LINEAR,
67 MSP_PHASE2_START_MODE_FSYNC,
68 MSP_PHASE2_START_MODE_FSYNC,
87 MSP_COMPRESS_MODE_LINEAR,
88 MSP_EXPAND_MODE_LINEAR,
93 }, { /* Companded PCM */
96 MSP_PHASE2_START_MODE_FSYNC,
97 MSP_PHASE2_START_MODE_FSYNC,
112 MSP_FSYNC_POL_ACT_HI,
113 MSP_FSYNC_POL_ACT_HI,
116 MSP_COMPRESS_MODE_LINEAR,
117 MSP_EXPAND_MODE_LINEAR,
125 static void set_prot_desc_tx(struct ux500_msp *msp,
126 struct msp_protdesc *protdesc,
127 enum msp_data_size data_size)
131 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode);
132 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode);
133 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1);
134 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2);
135 if (msp->def_elem_len) {
136 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1);
137 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2);
139 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
140 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
142 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay);
143 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order);
144 temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol);
145 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap);
146 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode);
147 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
149 writel(temp_reg, msp->registers + MSP_TCF);
152 static void set_prot_desc_rx(struct ux500_msp *msp,
153 struct msp_protdesc *protdesc,
154 enum msp_data_size data_size)
158 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode);
159 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode);
160 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1);
161 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2);
162 if (msp->def_elem_len) {
163 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1);
164 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2);
166 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
167 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
170 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay);
171 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order);
172 temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol);
173 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap);
174 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode);
175 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
177 writel(temp_reg, msp->registers + MSP_RCF);
180 static int configure_protocol(struct ux500_msp *msp,
181 struct ux500_msp_config *config)
183 struct msp_protdesc *protdesc;
184 enum msp_data_size data_size;
187 data_size = config->data_size;
188 msp->def_elem_len = config->def_elem_len;
189 if (config->default_protdesc == 1) {
190 if (config->protocol >= MSP_INVALID_PROTOCOL) {
191 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n",
196 (struct msp_protdesc *)&prot_descs[config->protocol];
198 protdesc = (struct msp_protdesc *)&config->protdesc;
201 if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) {
203 "%s: ERROR: Invalid data-size requested (data_size = %d)!\n",
204 __func__, data_size);
208 if (config->direction & MSP_DIR_TX)
209 set_prot_desc_tx(msp, protdesc, data_size);
210 if (config->direction & MSP_DIR_RX)
211 set_prot_desc_rx(msp, protdesc, data_size);
213 /* The code below should not be separated. */
214 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;
215 temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol);
216 writel(temp_reg, msp->registers + MSP_GCR);
217 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;
218 temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol);
219 writel(temp_reg, msp->registers + MSP_GCR);
224 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config)
231 struct msp_protdesc *protdesc = NULL;
233 reg_val_GCR = readl(msp->registers + MSP_GCR);
234 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
236 if (config->default_protdesc)
238 (struct msp_protdesc *)&prot_descs[config->protocol];
240 protdesc = (struct msp_protdesc *)&config->protdesc;
242 switch (config->protocol) {
243 case MSP_PCM_PROTOCOL:
244 case MSP_PCM_COMPAND_PROTOCOL:
245 frame_width = protdesc->frame_width;
246 sck_div = config->f_inputclk / (config->frame_freq *
247 (protdesc->clocks_per_frame));
248 frame_per = protdesc->frame_period;
250 case MSP_I2S_PROTOCOL:
251 frame_width = protdesc->frame_width;
252 sck_div = config->f_inputclk / (config->frame_freq *
253 (protdesc->clocks_per_frame));
254 frame_per = protdesc->frame_period;
257 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n",
263 temp_reg = (sck_div - 1) & SCK_DIV_MASK;
264 temp_reg |= FRAME_WIDTH_BITS(frame_width);
265 temp_reg |= FRAME_PERIOD_BITS(frame_per);
266 writel(temp_reg, msp->registers + MSP_SRG);
268 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1);
270 /* Enable bit-clock */
272 reg_val_GCR = readl(msp->registers + MSP_GCR);
273 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
279 static int configure_multichannel(struct ux500_msp *msp,
280 struct ux500_msp_config *config)
282 struct msp_protdesc *protdesc;
283 struct msp_multichannel_config *mcfg;
286 if (config->default_protdesc == 1) {
287 if (config->protocol >= MSP_INVALID_PROTOCOL) {
289 "%s: ERROR: Invalid protocol (%d)!\n",
290 __func__, config->protocol);
293 protdesc = (struct msp_protdesc *)
294 &prot_descs[config->protocol];
296 protdesc = (struct msp_protdesc *)&config->protdesc;
299 mcfg = &config->multichannel_config;
300 if (mcfg->tx_multichannel_enable) {
301 if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) {
302 reg_val_MCR = readl(msp->registers + MSP_MCR);
303 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ?
305 msp->registers + MSP_MCR);
306 writel(mcfg->tx_channel_0_enable,
307 msp->registers + MSP_TCE0);
308 writel(mcfg->tx_channel_1_enable,
309 msp->registers + MSP_TCE1);
310 writel(mcfg->tx_channel_2_enable,
311 msp->registers + MSP_TCE2);
312 writel(mcfg->tx_channel_3_enable,
313 msp->registers + MSP_TCE3);
316 "%s: ERROR: Only single-phase supported (TX-mode: %d)!\n",
317 __func__, protdesc->tx_phase_mode);
321 if (mcfg->rx_multichannel_enable) {
322 if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) {
323 reg_val_MCR = readl(msp->registers + MSP_MCR);
324 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ?
326 msp->registers + MSP_MCR);
327 writel(mcfg->rx_channel_0_enable,
328 msp->registers + MSP_RCE0);
329 writel(mcfg->rx_channel_1_enable,
330 msp->registers + MSP_RCE1);
331 writel(mcfg->rx_channel_2_enable,
332 msp->registers + MSP_RCE2);
333 writel(mcfg->rx_channel_3_enable,
334 msp->registers + MSP_RCE3);
337 "%s: ERROR: Only single-phase supported (RX-mode: %d)!\n",
338 __func__, protdesc->rx_phase_mode);
341 if (mcfg->rx_comparison_enable_mode) {
342 reg_val_MCR = readl(msp->registers + MSP_MCR);
344 (mcfg->rx_comparison_enable_mode << RCMPM_BIT),
345 msp->registers + MSP_MCR);
347 writel(mcfg->comparison_mask,
348 msp->registers + MSP_RCM);
349 writel(mcfg->comparison_value,
350 msp->registers + MSP_RCV);
358 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
360 int status = 0, retval = 0;
361 u32 reg_val_DMACR, reg_val_GCR;
364 /* Check msp state whether in RUN or CONFIGURED Mode */
365 if (msp->msp_state == MSP_STATE_IDLE) {
366 spin_lock_irqsave(&msp_rxtx_lock, flags);
367 if (msp->pinctrl_rxtx_ref == 0 &&
368 !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_def))) {
369 retval = pinctrl_select_state(msp->pinctrl_p,
372 pr_err("could not set MSP defstate\n");
375 msp->pinctrl_rxtx_ref++;
376 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
379 /* Configure msp with protocol dependent settings */
380 configure_protocol(msp, config);
381 setup_bitclk(msp, config);
382 if (config->multichannel_configured == 1) {
383 status = configure_multichannel(msp, config);
386 "%s: WARN: configure_multichannel failed (%d)!\n",
390 /* Make sure the correct DMA-directions are configured */
391 if ((config->direction & MSP_DIR_RX) && (!msp->dma_cfg_rx)) {
392 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!",
396 if ((config->direction == MSP_DIR_TX) && (!msp->dma_cfg_tx)) {
397 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!",
402 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
403 if (config->direction & MSP_DIR_RX)
404 reg_val_DMACR |= RX_DMA_ENABLE;
405 if (config->direction & MSP_DIR_TX)
406 reg_val_DMACR |= TX_DMA_ENABLE;
407 writel(reg_val_DMACR, msp->registers + MSP_DMACR);
409 writel(config->iodelay, msp->registers + MSP_IODLY);
411 /* Enable frame generation logic */
412 reg_val_GCR = readl(msp->registers + MSP_GCR);
413 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
418 static void flush_fifo_rx(struct ux500_msp *msp)
420 u32 reg_val_DR, reg_val_GCR, reg_val_FLR;
423 reg_val_GCR = readl(msp->registers + MSP_GCR);
424 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
426 reg_val_FLR = readl(msp->registers + MSP_FLR);
427 while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
428 reg_val_DR = readl(msp->registers + MSP_DR);
429 reg_val_FLR = readl(msp->registers + MSP_FLR);
432 writel(reg_val_GCR, msp->registers + MSP_GCR);
435 static void flush_fifo_tx(struct ux500_msp *msp)
437 u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR;
440 reg_val_GCR = readl(msp->registers + MSP_GCR);
441 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
442 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
444 reg_val_FLR = readl(msp->registers + MSP_FLR);
445 while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
446 reg_val_TSTDR = readl(msp->registers + MSP_TSTDR);
447 reg_val_FLR = readl(msp->registers + MSP_FLR);
449 writel(0x0, msp->registers + MSP_ITCR);
450 writel(reg_val_GCR, msp->registers + MSP_GCR);
453 int ux500_msp_i2s_open(struct ux500_msp *msp,
454 struct ux500_msp_config *config)
456 u32 old_reg, new_reg, mask;
458 unsigned int tx_sel, rx_sel, tx_busy, rx_busy;
460 if (in_interrupt()) {
462 "%s: ERROR: Open called in interrupt context!\n",
467 tx_sel = (config->direction & MSP_DIR_TX) > 0;
468 rx_sel = (config->direction & MSP_DIR_RX) > 0;
469 if (!tx_sel && !rx_sel) {
470 dev_err(msp->dev, "%s: Error: No direction selected!\n",
475 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0;
476 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0;
477 if (tx_busy && tx_sel) {
478 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__);
481 if (rx_busy && rx_sel) {
482 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__);
486 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
488 /* First do the global config register */
489 mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK |
490 TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK |
491 RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK |
492 LOOPBACK_MASK | TX_EXTRA_DELAY_MASK;
494 new_reg = (config->tx_clk_sel | config->rx_clk_sel |
495 config->rx_fsync_pol | config->tx_fsync_pol |
496 config->rx_fsync_sel | config->tx_fsync_sel |
497 config->rx_fifo_config | config->tx_fifo_config |
498 config->srg_clk_sel | config->loopback_enable |
499 config->tx_data_enable);
501 old_reg = readl(msp->registers + MSP_GCR);
504 writel(new_reg, msp->registers + MSP_GCR);
506 res = enable_msp(msp, config);
508 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
512 if (config->loopback_enable & 0x80)
513 msp->loopback_enable = 1;
519 msp->msp_state = MSP_STATE_CONFIGURED;
523 static void disable_msp_rx(struct ux500_msp *msp)
525 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
527 reg_val_GCR = readl(msp->registers + MSP_GCR);
528 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
529 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
530 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
531 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
532 writel(reg_val_IMSC &
533 ~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT),
534 msp->registers + MSP_IMSC);
536 msp->dir_busy &= ~MSP_DIR_RX;
539 static void disable_msp_tx(struct ux500_msp *msp)
541 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
543 reg_val_GCR = readl(msp->registers + MSP_GCR);
544 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
545 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
546 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
547 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
548 writel(reg_val_IMSC &
549 ~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT),
550 msp->registers + MSP_IMSC);
552 msp->dir_busy &= ~MSP_DIR_TX;
555 static int disable_msp(struct ux500_msp *msp, unsigned int dir)
559 unsigned int disable_tx, disable_rx;
561 reg_val_GCR = readl(msp->registers + MSP_GCR);
562 disable_tx = dir & MSP_DIR_TX;
563 disable_rx = dir & MSP_DIR_TX;
564 if (disable_tx && disable_rx) {
565 reg_val_GCR = readl(msp->registers + MSP_GCR);
566 writel(reg_val_GCR | LOOPBACK_MASK,
567 msp->registers + MSP_GCR);
572 /* Disable TX-channel */
573 writel((readl(msp->registers + MSP_GCR) &
574 (~TX_ENABLE)), msp->registers + MSP_GCR);
579 /* Disable Loopback and Receive channel */
580 writel((readl(msp->registers + MSP_GCR) &
581 (~(RX_ENABLE | LOOPBACK_MASK))),
582 msp->registers + MSP_GCR);
586 } else if (disable_tx)
594 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
596 u32 reg_val_GCR, enable_bit;
598 if (msp->msp_state == MSP_STATE_IDLE) {
599 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
605 case SNDRV_PCM_TRIGGER_START:
606 case SNDRV_PCM_TRIGGER_RESUME:
607 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
608 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
609 enable_bit = TX_ENABLE;
611 enable_bit = RX_ENABLE;
612 reg_val_GCR = readl(msp->registers + MSP_GCR);
613 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
616 case SNDRV_PCM_TRIGGER_STOP:
617 case SNDRV_PCM_TRIGGER_SUSPEND:
618 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
619 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
632 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
634 int status = 0, retval = 0;
637 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
639 status = disable_msp(msp, dir);
640 if (msp->dir_busy == 0) {
641 /* disable sample rate and frame generators */
642 msp->msp_state = MSP_STATE_IDLE;
643 writel((readl(msp->registers + MSP_GCR) &
644 (~(FRAME_GEN_ENABLE | SRG_ENABLE))),
645 msp->registers + MSP_GCR);
647 spin_lock_irqsave(&msp_rxtx_lock, flags);
648 WARN_ON(!msp->pinctrl_rxtx_ref);
649 msp->pinctrl_rxtx_ref--;
650 if (msp->pinctrl_rxtx_ref == 0 &&
651 !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_sleep))) {
652 retval = pinctrl_select_state(msp->pinctrl_p,
655 pr_err("could not set MSP sleepstate\n");
657 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
659 writel(0, msp->registers + MSP_GCR);
660 writel(0, msp->registers + MSP_TCF);
661 writel(0, msp->registers + MSP_RCF);
662 writel(0, msp->registers + MSP_DMACR);
663 writel(0, msp->registers + MSP_SRG);
664 writel(0, msp->registers + MSP_MCR);
665 writel(0, msp->registers + MSP_RCM);
666 writel(0, msp->registers + MSP_RCV);
667 writel(0, msp->registers + MSP_TCE0);
668 writel(0, msp->registers + MSP_TCE1);
669 writel(0, msp->registers + MSP_TCE2);
670 writel(0, msp->registers + MSP_TCE3);
671 writel(0, msp->registers + MSP_RCE0);
672 writel(0, msp->registers + MSP_RCE1);
673 writel(0, msp->registers + MSP_RCE2);
674 writel(0, msp->registers + MSP_RCE3);
681 int ux500_msp_i2s_init_msp(struct platform_device *pdev,
682 struct ux500_msp **msp_p,
683 struct msp_i2s_platform_data *platform_data)
685 struct resource *res = NULL;
686 struct i2s_controller *i2s_cont;
687 struct device_node *np = pdev->dev.of_node;
688 struct ux500_msp *msp;
690 *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
694 if (!platform_data) {
695 platform_data = devm_kzalloc(&pdev->dev,
696 sizeof(struct msp_i2s_platform_data), GFP_KERNEL);
707 dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
708 pdev->name, platform_data->id);
710 msp->id = platform_data->id;
711 msp->dev = &pdev->dev;
712 msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
713 msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx;
715 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
717 dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n",
722 msp->registers = devm_ioremap(&pdev->dev, res->start,
724 if (msp->registers == NULL) {
725 dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__);
729 msp->msp_state = MSP_STATE_IDLE;
730 msp->loopback_enable = 0;
732 /* I2S-controller is allocated and added in I2S controller class. */
733 i2s_cont = devm_kzalloc(&pdev->dev, sizeof(*i2s_cont), GFP_KERNEL);
736 "%s: ERROR: Failed to allocate I2S-controller!\n",
740 i2s_cont->dev.parent = &pdev->dev;
741 i2s_cont->data = (void *)msp;
742 i2s_cont->id = (s16)msp->id;
743 snprintf(i2s_cont->name, sizeof(i2s_cont->name), "ux500-msp-i2s.%04x",
745 dev_dbg(&pdev->dev, "I2S device-name: '%s'\n", i2s_cont->name);
746 msp->i2s_cont = i2s_cont;
748 msp->pinctrl_p = pinctrl_get(msp->dev);
749 if (IS_ERR(msp->pinctrl_p))
750 dev_err(&pdev->dev, "could not get MSP pinctrl\n");
752 msp->pinctrl_def = pinctrl_lookup_state(msp->pinctrl_p,
753 PINCTRL_STATE_DEFAULT);
754 if (IS_ERR(msp->pinctrl_def)) {
756 "could not get MSP defstate (%li)\n",
757 PTR_ERR(msp->pinctrl_def));
759 msp->pinctrl_sleep = pinctrl_lookup_state(msp->pinctrl_p,
760 PINCTRL_STATE_SLEEP);
761 if (IS_ERR(msp->pinctrl_sleep))
763 "could not get MSP idlestate (%li)\n",
764 PTR_ERR(msp->pinctrl_def));
770 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
771 struct ux500_msp *msp)
773 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id);
775 device_unregister(&msp->i2s_cont->dev);
778 MODULE_LICENSE("GPL v2");