sound/x86/intel_hdmi_audio.c

   1 /*
   2  *   intel_hdmi_audio.c - Intel HDMI audio driver
   3  *
   4  *  Copyright (C) 2016 Intel Corp
   5  *  Authors:    Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
   6  *              Ramesh Babu K V <ramesh.babu@intel.com>
   7  *              Vaibhav Agarwal <vaibhav.agarwal@intel.com>
   8  *              Jerome Anand <jerome.anand@intel.com>
   9  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; version 2 of the License.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but
  16  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  *  General Public License for more details.
  19  *
  20  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  21  * ALSA driver for Intel HDMI audio
  22  */
  23
  24 #include <linux/types.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/io.h>
  27 #include <linux/slab.h>
  28 #include <linux/module.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <asm/cacheflush.h>
  34 #include <sound/core.h>
  35 #include <sound/asoundef.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/initval.h>
  39 #include <sound/control.h>
  40 #include <sound/jack.h>
  41 #include <drm/drm_edid.h>
  42 #include <drm/intel_lpe_audio.h>
  43 #include "intel_hdmi_audio.h"
  44
  45 #define for_each_port(card_ctx, port) \
  46         for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++)
  47
  48 /*standard module options for ALSA. This module supports only one card*/
  49 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
  50 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
  51
  52 module_param_named(index, hdmi_card_index, int, 0444);
  53 MODULE_PARM_DESC(index,
  54                 "Index value for INTEL Intel HDMI Audio controller.");
  55 module_param_named(id, hdmi_card_id, charp, 0444);
  56 MODULE_PARM_DESC(id,
  57                 "ID string for INTEL Intel HDMI Audio controller.");
  58
  59 /*
  60  * ELD SA bits in the CEA Speaker Allocation data block
  61  */
  62 static const int eld_speaker_allocation_bits[] = {
  63         [0] = FL | FR,
  64         [1] = LFE,
  65         [2] = FC,
  66         [3] = RL | RR,
  67         [4] = RC,
  68         [5] = FLC | FRC,
  69         [6] = RLC | RRC,
  70         /* the following are not defined in ELD yet */
  71         [7] = 0,
  72 };
  73
  74 /*
  75  * This is an ordered list!
  76  *
  77  * The preceding ones have better chances to be selected by
  78  * hdmi_channel_allocation().
  79  */
  80 static struct cea_channel_speaker_allocation channel_allocations[] = {
  81 /*                        channel:   7     6    5    4    3     2    1    0  */
  82 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
  83                                 /* 2.1 */
  84 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
  85                                 /* Dolby Surround */
  86 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
  87                                 /* surround40 */
  88 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
  89                                 /* surround41 */
  90 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
  91                                 /* surround50 */
  92 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
  93                                 /* surround51 */
  94 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
  95                                 /* 6.1 */
  96 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
  97                                 /* surround71 */
  98 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
  99
 100 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
 101 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
 102 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
 103 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
 104 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
 105 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
 106 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
 107 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 108 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
 109 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 110 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
 111 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
 112 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
 113 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
 114 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
 115 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
 116 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
 117 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
 118 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
 119 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
 120 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 121 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
 122 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 123 };
 124
 125 static const struct channel_map_table map_tables[] = {
 126         { SNDRV_CHMAP_FL,       0x00,   FL },
 127         { SNDRV_CHMAP_FR,       0x01,   FR },
 128         { SNDRV_CHMAP_RL,       0x04,   RL },
 129         { SNDRV_CHMAP_RR,       0x05,   RR },
 130         { SNDRV_CHMAP_LFE,      0x02,   LFE },
 131         { SNDRV_CHMAP_FC,       0x03,   FC },
 132         { SNDRV_CHMAP_RLC,      0x06,   RLC },
 133         { SNDRV_CHMAP_RRC,      0x07,   RRC },
 134         {} /* terminator */
 135 };
 136
 137 /* hardware capability structure */
 138 static const struct snd_pcm_hardware had_pcm_hardware = {
 139         .info = (SNDRV_PCM_INFO_INTERLEAVED |
 140                 SNDRV_PCM_INFO_MMAP |
 141                 SNDRV_PCM_INFO_MMAP_VALID |
 142                 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 143         .formats = (SNDRV_PCM_FMTBIT_S16_LE |
 144                     SNDRV_PCM_FMTBIT_S24_LE |
 145                     SNDRV_PCM_FMTBIT_S32_LE),
 146         .rates = SNDRV_PCM_RATE_32000 |
 147                 SNDRV_PCM_RATE_44100 |
 148                 SNDRV_PCM_RATE_48000 |
 149                 SNDRV_PCM_RATE_88200 |
 150                 SNDRV_PCM_RATE_96000 |
 151                 SNDRV_PCM_RATE_176400 |
 152                 SNDRV_PCM_RATE_192000,
 153         .rate_min = HAD_MIN_RATE,
 154         .rate_max = HAD_MAX_RATE,
 155         .channels_min = HAD_MIN_CHANNEL,
 156         .channels_max = HAD_MAX_CHANNEL,
 157         .buffer_bytes_max = HAD_MAX_BUFFER,
 158         .period_bytes_min = HAD_MIN_PERIOD_BYTES,
 159         .period_bytes_max = HAD_MAX_PERIOD_BYTES,
 160         .periods_min = HAD_MIN_PERIODS,
 161         .periods_max = HAD_MAX_PERIODS,
 162         .fifo_size = HAD_FIFO_SIZE,
 163 };
 164
 165 /* Get the active PCM substream;
 166  * Call had_substream_put() for unreferecing.
 167  * Don't call this inside had_spinlock, as it takes by itself
 168  */
 169 static struct snd_pcm_substream *
 170 had_substream_get(struct snd_intelhad *intelhaddata)
 171 {
 172         struct snd_pcm_substream *substream;
 173         unsigned long flags;
 174
 175         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 176         substream = intelhaddata->stream_info.substream;
 177         if (substream)
 178                 intelhaddata->stream_info.substream_refcount++;
 179         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 180         return substream;
 181 }
 182
 183 /* Unref the active PCM substream;
 184  * Don't call this inside had_spinlock, as it takes by itself
 185  */
 186 static void had_substream_put(struct snd_intelhad *intelhaddata)
 187 {
 188         unsigned long flags;
 189
 190         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 191         intelhaddata->stream_info.substream_refcount--;
 192         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 193 }
 194
 195 /* Register access functions */
 196 static u32 had_read_register_raw(struct snd_intelhad *ctx, u32 reg)
 197 {
 198         return ioread32(ctx->card_ctx->mmio_start + ctx->had_config_offset + reg);
 199 }
 200
 201 static void had_write_register_raw(struct snd_intelhad *ctx, u32 reg, u32 val)
 202 {
 203         iowrite32(val, ctx->card_ctx->mmio_start + ctx->had_config_offset + reg);
 204 }
 205
 206 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
 207 {
 208         if (!ctx->connected)
 209                 *val = 0;
 210         else
 211                 *val = had_read_register_raw(ctx, reg);
 212 }
 213
 214 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
 215 {
 216         if (ctx->connected)
 217                 had_write_register_raw(ctx, reg, val);
 218 }
 219
 220 /*
 221  * enable / disable audio configuration
 222  *
 223  * The normal read/modify should not directly be used on VLV2 for
 224  * updating AUD_CONFIG register.
 225  * This is because:
 226  * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
 227  * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
 228  * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
 229  * register. This field should be 1xy binary for configuration with 6 or
 230  * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
 231  * causes the "channels" field to be updated as 0xy binary resulting in
 232  * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
 233  * appropriate value when doing read-modify of AUD_CONFIG register.
 234  */
 235 static void had_enable_audio(struct snd_intelhad *intelhaddata,
 236                              bool enable)
 237 {
 238         /* update the cached value */
 239         intelhaddata->aud_config.regx.aud_en = enable;
 240         had_write_register(intelhaddata, AUD_CONFIG,
 241                            intelhaddata->aud_config.regval);
 242 }
 243
 244 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
 245 static void had_ack_irqs(struct snd_intelhad *ctx)
 246 {
 247         u32 status_reg;
 248
 249         if (!ctx->connected)
 250                 return;
 251         had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
 252         status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
 253         had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
 254         had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
 255 }
 256
 257 /* Reset buffer pointers */
 258 static void had_reset_audio(struct snd_intelhad *intelhaddata)
 259 {
 260         had_write_register(intelhaddata, AUD_HDMI_STATUS,
 261                            AUD_HDMI_STATUSG_MASK_FUNCRST);
 262         had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
 263 }
 264
 265 /*
 266  * initialize audio channel status registers
 267  * This function is called in the prepare callback
 268  */
 269 static int had_prog_status_reg(struct snd_pcm_substream *substream,
 270                         struct snd_intelhad *intelhaddata)
 271 {
 272         union aud_cfg cfg_val = {.regval = 0};
 273         union aud_ch_status_0 ch_stat0 = {.regval = 0};
 274         union aud_ch_status_1 ch_stat1 = {.regval = 0};
 275
 276         ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
 277                                           IEC958_AES0_NONAUDIO) >> 1;
 278         ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
 279                                           IEC958_AES3_CON_CLOCK) >> 4;
 280         cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id;
 281
 282         switch (substream->runtime->rate) {
 283         case AUD_SAMPLE_RATE_32:
 284                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
 285                 break;
 286
 287         case AUD_SAMPLE_RATE_44_1:
 288                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
 289                 break;
 290         case AUD_SAMPLE_RATE_48:
 291                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
 292                 break;
 293         case AUD_SAMPLE_RATE_88_2:
 294                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
 295                 break;
 296         case AUD_SAMPLE_RATE_96:
 297                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
 298                 break;
 299         case AUD_SAMPLE_RATE_176_4:
 300                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
 301                 break;
 302         case AUD_SAMPLE_RATE_192:
 303                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
 304                 break;
 305
 306         default:
 307                 /* control should never come here */
 308                 return -EINVAL;
 309         }
 310
 311         had_write_register(intelhaddata,
 312                            AUD_CH_STATUS_0, ch_stat0.regval);
 313
 314         switch (substream->runtime->format) {
 315         case SNDRV_PCM_FORMAT_S16_LE:
 316                 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
 317                 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
 318                 break;
 319         case SNDRV_PCM_FORMAT_S24_LE:
 320         case SNDRV_PCM_FORMAT_S32_LE:
 321                 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
 322                 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
 323                 break;
 324         default:
 325                 return -EINVAL;
 326         }
 327
 328         had_write_register(intelhaddata,
 329                            AUD_CH_STATUS_1, ch_stat1.regval);
 330         return 0;
 331 }
 332
 333 /*
 334  * function to initialize audio
 335  * registers and buffer confgiuration registers
 336  * This function is called in the prepare callback
 337  */
 338 static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
 339                                struct snd_intelhad *intelhaddata)
 340 {
 341         union aud_cfg cfg_val = {.regval = 0};
 342         union aud_buf_config buf_cfg = {.regval = 0};
 343         u8 channels;
 344
 345         had_prog_status_reg(substream, intelhaddata);
 346
 347         buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
 348         buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
 349         buf_cfg.regx.aud_delay = 0;
 350         had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
 351
 352         channels = substream->runtime->channels;
 353         cfg_val.regx.num_ch = channels - 2;
 354         if (channels <= 2)
 355                 cfg_val.regx.layout = LAYOUT0;
 356         else
 357                 cfg_val.regx.layout = LAYOUT1;
 358
 359         if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
 360                 cfg_val.regx.packet_mode = 1;
 361
 362         if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
 363                 cfg_val.regx.left_align = 1;
 364
 365         cfg_val.regx.val_bit = 1;
 366
 367         /* fix up the DP bits */
 368         if (intelhaddata->dp_output) {
 369                 cfg_val.regx.dp_modei = 1;
 370                 cfg_val.regx.set = 1;
 371         }
 372
 373         had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
 374         intelhaddata->aud_config = cfg_val;
 375         return 0;
 376 }
 377
 378 /*
 379  * Compute derived values in channel_allocations[].
 380  */
 381 static void init_channel_allocations(void)
 382 {
 383         int i, j;
 384         struct cea_channel_speaker_allocation *p;
 385
 386         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 387                 p = channel_allocations + i;
 388                 p->channels = 0;
 389                 p->spk_mask = 0;
 390                 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
 391                         if (p->speakers[j]) {
 392                                 p->channels++;
 393                                 p->spk_mask |= p->speakers[j];
 394                         }
 395         }
 396 }
 397
 398 /*
 399  * The transformation takes two steps:
 400  *
 401  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
 402  *            spk_mask => (channel_allocations[])         => ai->CA
 403  *
 404  * TODO: it could select the wrong CA from multiple candidates.
 405  */
 406 static int had_channel_allocation(struct snd_intelhad *intelhaddata,
 407                                   int channels)
 408 {
 409         int i;
 410         int ca = 0;
 411         int spk_mask = 0;
 412
 413         /*
 414          * CA defaults to 0 for basic stereo audio
 415          */
 416         if (channels <= 2)
 417                 return 0;
 418
 419         /*
 420          * expand ELD's speaker allocation mask
 421          *
 422          * ELD tells the speaker mask in a compact(paired) form,
 423          * expand ELD's notions to match the ones used by Audio InfoFrame.
 424          */
 425
 426         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 427                 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
 428                         spk_mask |= eld_speaker_allocation_bits[i];
 429         }
 430
 431         /* search for the first working match in the CA table */
 432         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 433                 if (channels == channel_allocations[i].channels &&
 434                 (spk_mask & channel_allocations[i].spk_mask) ==
 435                                 channel_allocations[i].spk_mask) {
 436                         ca = channel_allocations[i].ca_index;
 437                         break;
 438                 }
 439         }
 440
 441         dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
 442
 443         return ca;
 444 }
 445
 446 /* from speaker bit mask to ALSA API channel position */
 447 static int spk_to_chmap(int spk)
 448 {
 449         const struct channel_map_table *t = map_tables;
 450
 451         for (; t->map; t++) {
 452                 if (t->spk_mask == spk)
 453                         return t->map;
 454         }
 455         return 0;
 456 }
 457
 458 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
 459 {
 460         int i, c;
 461         int spk_mask = 0;
 462         struct snd_pcm_chmap_elem *chmap;
 463         u8 eld_high, eld_high_mask = 0xF0;
 464         u8 high_msb;
 465
 466         kfree(intelhaddata->chmap->chmap);
 467         intelhaddata->chmap->chmap = NULL;
 468
 469         chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
 470         if (!chmap)
 471                 return;
 472
 473         dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
 474                 intelhaddata->eld[DRM_ELD_SPEAKER]);
 475
 476         /* WA: Fix the max channel supported to 8 */
 477
 478         /*
 479          * Sink may support more than 8 channels, if eld_high has more than
 480          * one bit set. SOC supports max 8 channels.
 481          * Refer eld_speaker_allocation_bits, for sink speaker allocation
 482          */
 483
 484         /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
 485         eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
 486         if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
 487                 /* eld_high & (eld_high-1): if more than 1 bit set */
 488                 /* 0x1F: 7 channels */
 489                 for (i = 1; i < 4; i++) {
 490                         high_msb = eld_high & (0x80 >> i);
 491                         if (high_msb) {
 492                                 intelhaddata->eld[DRM_ELD_SPEAKER] &=
 493                                         high_msb | 0xF;
 494                                 break;
 495                         }
 496                 }
 497         }
 498
 499         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 500                 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
 501                         spk_mask |= eld_speaker_allocation_bits[i];
 502         }
 503
 504         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 505                 if (spk_mask == channel_allocations[i].spk_mask) {
 506                         for (c = 0; c < channel_allocations[i].channels; c++) {
 507                                 chmap->map[c] = spk_to_chmap(
 508                                         channel_allocations[i].speakers[
 509                                                 (MAX_SPEAKERS - 1) - c]);
 510                         }
 511                         chmap->channels = channel_allocations[i].channels;
 512                         intelhaddata->chmap->chmap = chmap;
 513                         break;
 514                 }
 515         }
 516         if (i >= ARRAY_SIZE(channel_allocations))
 517                 kfree(chmap);
 518 }
 519
 520 /*
 521  * ALSA API channel-map control callbacks
 522  */
 523 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
 524                                 struct snd_ctl_elem_info *uinfo)
 525 {
 526         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 527         uinfo->count = HAD_MAX_CHANNEL;
 528         uinfo->value.integer.min = 0;
 529         uinfo->value.integer.max = SNDRV_CHMAP_LAST;
 530         return 0;
 531 }
 532
 533 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
 534                                 struct snd_ctl_elem_value *ucontrol)
 535 {
 536         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
 537         struct snd_intelhad *intelhaddata = info->private_data;
 538         int i;
 539         const struct snd_pcm_chmap_elem *chmap;
 540
 541         memset(ucontrol->value.integer.value, 0,
 542                sizeof(long) * HAD_MAX_CHANNEL);
 543         mutex_lock(&intelhaddata->mutex);
 544         if (!intelhaddata->chmap->chmap) {
 545                 mutex_unlock(&intelhaddata->mutex);
 546                 return 0;
 547         }
 548
 549         chmap = intelhaddata->chmap->chmap;
 550         for (i = 0; i < chmap->channels; i++)
 551                 ucontrol->value.integer.value[i] = chmap->map[i];
 552         mutex_unlock(&intelhaddata->mutex);
 553
 554         return 0;
 555 }
 556
 557 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
 558                                                 struct snd_pcm *pcm)
 559 {
 560         int err;
 561
 562         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
 563                         NULL, 0, (unsigned long)intelhaddata,
 564                         &intelhaddata->chmap);
 565         if (err < 0)
 566                 return err;
 567
 568         intelhaddata->chmap->private_data = intelhaddata;
 569         intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
 570         intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
 571         intelhaddata->chmap->chmap = NULL;
 572         return 0;
 573 }
 574
 575 /*
 576  * Initialize Data Island Packets registers
 577  * This function is called in the prepare callback
 578  */
 579 static void had_prog_dip(struct snd_pcm_substream *substream,
 580                          struct snd_intelhad *intelhaddata)
 581 {
 582         int i;
 583         union aud_ctrl_st ctrl_state = {.regval = 0};
 584         union aud_info_frame2 frame2 = {.regval = 0};
 585         union aud_info_frame3 frame3 = {.regval = 0};
 586         u8 checksum = 0;
 587         u32 info_frame;
 588         int channels;
 589         int ca;
 590
 591         channels = substream->runtime->channels;
 592
 593         had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
 594
 595         ca = had_channel_allocation(intelhaddata, channels);
 596         if (intelhaddata->dp_output) {
 597                 info_frame = DP_INFO_FRAME_WORD1;
 598                 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
 599         } else {
 600                 info_frame = HDMI_INFO_FRAME_WORD1;
 601                 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
 602                 frame3.regx.chnl_alloc = ca;
 603
 604                 /* Calculte the byte wide checksum for all valid DIP words */
 605                 for (i = 0; i < BYTES_PER_WORD; i++)
 606                         checksum += (info_frame >> (i * 8)) & 0xff;
 607                 for (i = 0; i < BYTES_PER_WORD; i++)
 608                         checksum += (frame2.regval >> (i * 8)) & 0xff;
 609                 for (i = 0; i < BYTES_PER_WORD; i++)
 610                         checksum += (frame3.regval >> (i * 8)) & 0xff;
 611
 612                 frame2.regx.chksum = -(checksum);
 613         }
 614
 615         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
 616         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
 617         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
 618
 619         /* program remaining DIP words with zero */
 620         for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
 621                 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
 622
 623         ctrl_state.regx.dip_freq = 1;
 624         ctrl_state.regx.dip_en_sta = 1;
 625         had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
 626 }
 627
 628 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
 629 {
 630         u32 maud_val;
 631
 632         /* Select maud according to DP 1.2 spec */
 633         if (link_rate == DP_2_7_GHZ) {
 634                 switch (aud_samp_freq) {
 635                 case AUD_SAMPLE_RATE_32:
 636                         maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
 637                         break;
 638
 639                 case AUD_SAMPLE_RATE_44_1:
 640                         maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
 641                         break;
 642
 643                 case AUD_SAMPLE_RATE_48:
 644                         maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
 645                         break;
 646
 647                 case AUD_SAMPLE_RATE_88_2:
 648                         maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
 649                         break;
 650
 651                 case AUD_SAMPLE_RATE_96:
 652                         maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
 653                         break;
 654
 655                 case AUD_SAMPLE_RATE_176_4:
 656                         maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
 657                         break;
 658
 659                 case HAD_MAX_RATE:
 660                         maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
 661                         break;
 662
 663                 default:
 664                         maud_val = -EINVAL;
 665                         break;
 666                 }
 667         } else if (link_rate == DP_1_62_GHZ) {
 668                 switch (aud_samp_freq) {
 669                 case AUD_SAMPLE_RATE_32:
 670                         maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
 671                         break;
 672
 673                 case AUD_SAMPLE_RATE_44_1:
 674                         maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
 675                         break;
 676
 677                 case AUD_SAMPLE_RATE_48:
 678                         maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
 679                         break;
 680
 681                 case AUD_SAMPLE_RATE_88_2:
 682                         maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
 683                         break;
 684
 685                 case AUD_SAMPLE_RATE_96:
 686                         maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
 687                         break;
 688
 689                 case AUD_SAMPLE_RATE_176_4:
 690                         maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
 691                         break;
 692
 693                 case HAD_MAX_RATE:
 694                         maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
 695                         break;
 696
 697                 default:
 698                         maud_val = -EINVAL;
 699                         break;
 700                 }
 701         } else
 702                 maud_val = -EINVAL;
 703
 704         return maud_val;
 705 }
 706
 707 /*
 708  * Program HDMI audio CTS value
 709  *
 710  * @aud_samp_freq: sampling frequency of audio data
 711  * @tmds: sampling frequency of the display data
 712  * @link_rate: DP link rate
 713  * @n_param: N value, depends on aud_samp_freq
 714  * @intelhaddata: substream private data
 715  *
 716  * Program CTS register based on the audio and display sampling frequency
 717  */
 718 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
 719                          u32 n_param, struct snd_intelhad *intelhaddata)
 720 {
 721         u32 cts_val;
 722         u64 dividend, divisor;
 723
 724         if (intelhaddata->dp_output) {
 725                 /* Substitute cts_val with Maud according to DP 1.2 spec*/
 726                 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
 727         } else {
 728                 /* Calculate CTS according to HDMI 1.3a spec*/
 729                 dividend = (u64)tmds * n_param*1000;
 730                 divisor = 128 * aud_samp_freq;
 731                 cts_val = div64_u64(dividend, divisor);
 732         }
 733         dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
 734                  tmds, n_param, cts_val);
 735         had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
 736 }
 737
 738 static int had_calculate_n_value(u32 aud_samp_freq)
 739 {
 740         int n_val;
 741
 742         /* Select N according to HDMI 1.3a spec*/
 743         switch (aud_samp_freq) {
 744         case AUD_SAMPLE_RATE_32:
 745                 n_val = 4096;
 746                 break;
 747
 748         case AUD_SAMPLE_RATE_44_1:
 749                 n_val = 6272;
 750                 break;
 751
 752         case AUD_SAMPLE_RATE_48:
 753                 n_val = 6144;
 754                 break;
 755
 756         case AUD_SAMPLE_RATE_88_2:
 757                 n_val = 12544;
 758                 break;
 759
 760         case AUD_SAMPLE_RATE_96:
 761                 n_val = 12288;
 762                 break;
 763
 764         case AUD_SAMPLE_RATE_176_4:
 765                 n_val = 25088;
 766                 break;
 767
 768         case HAD_MAX_RATE:
 769                 n_val = 24576;
 770                 break;
 771
 772         default:
 773                 n_val = -EINVAL;
 774                 break;
 775         }
 776         return n_val;
 777 }
 778
 779 /*
 780  * Program HDMI audio N value
 781  *
 782  * @aud_samp_freq: sampling frequency of audio data
 783  * @n_param: N value, depends on aud_samp_freq
 784  * @intelhaddata: substream private data
 785  *
 786  * This function is called in the prepare callback.
 787  * It programs based on the audio and display sampling frequency
 788  */
 789 static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
 790                       struct snd_intelhad *intelhaddata)
 791 {
 792         int n_val;
 793
 794         if (intelhaddata->dp_output) {
 795                 /*
 796                  * According to DP specs, Maud and Naud values hold
 797                  * a relationship, which is stated as:
 798                  * Maud/Naud = 512 * fs / f_LS_Clk
 799                  * where, fs is the sampling frequency of the audio stream
 800                  * and Naud is 32768 for Async clock.
 801                  */
 802
 803                 n_val = DP_NAUD_VAL;
 804         } else
 805                 n_val = had_calculate_n_value(aud_samp_freq);
 806
 807         if (n_val < 0)
 808                 return n_val;
 809
 810         had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
 811         *n_param = n_val;
 812         return 0;
 813 }
 814
 815 /*
 816  * PCM ring buffer handling
 817  *
 818  * The hardware provides a ring buffer with the fixed 4 buffer descriptors
 819  * (BDs).  The driver maps these 4 BDs onto the PCM ring buffer.  The mapping
 820  * moves at each period elapsed.  The below illustrates how it works:
 821  *
 822  * At time=0
 823  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 824  *  BD  | 0 | 1 | 2 | 3 |
 825  *
 826  * At time=1 (period elapsed)
 827  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 828  *  BD      | 1 | 2 | 3 | 0 |
 829  *
 830  * At time=2 (second period elapsed)
 831  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 832  *  BD          | 2 | 3 | 0 | 1 |
 833  *
 834  * The bd_head field points to the index of the BD to be read.  It's also the
 835  * position to be filled at next.  The pcm_head and the pcm_filled fields
 836  * point to the indices of the current position and of the next position to
 837  * be filled, respectively.  For PCM buffer there are both _head and _filled
 838  * because they may be difference when nperiods > 4.  For example, in the
 839  * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
 840  *
 841  * pcm_head (=1) --v               v-- pcm_filled (=5)
 842  *       PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 843  *       BD      | 1 | 2 | 3 | 0 |
 844  *  bd_head (=1) --^               ^-- next to fill (= bd_head)
 845  *
 846  * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
 847  * the hardware skips those BDs in the loop.
 848  *
 849  * An exceptional setup is the case with nperiods=1.  Since we have to update
 850  * BDs after finishing one BD processing, we'd need at least two BDs, where
 851  * both BDs point to the same content, the same address, the same size of the
 852  * whole PCM buffer.
 853  */
 854
 855 #define AUD_BUF_ADDR(x)         (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
 856 #define AUD_BUF_LEN(x)          (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
 857
 858 /* Set up a buffer descriptor at the "filled" position */
 859 static void had_prog_bd(struct snd_pcm_substream *substream,
 860                         struct snd_intelhad *intelhaddata)
 861 {
 862         int idx = intelhaddata->bd_head;
 863         int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
 864         u32 addr = substream->runtime->dma_addr + ofs;
 865
 866         addr |= AUD_BUF_VALID;
 867         if (!substream->runtime->no_period_wakeup)
 868                 addr |= AUD_BUF_INTR_EN;
 869         had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
 870         had_write_register(intelhaddata, AUD_BUF_LEN(idx),
 871                            intelhaddata->period_bytes);
 872
 873         /* advance the indices to the next */
 874         intelhaddata->bd_head++;
 875         intelhaddata->bd_head %= intelhaddata->num_bds;
 876         intelhaddata->pcmbuf_filled++;
 877         intelhaddata->pcmbuf_filled %= substream->runtime->periods;
 878 }
 879
 880 /* invalidate a buffer descriptor with the given index */
 881 static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
 882                               int idx)
 883 {
 884         had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
 885         had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
 886 }
 887
 888 /* Initial programming of ring buffer */
 889 static void had_init_ringbuf(struct snd_pcm_substream *substream,
 890                              struct snd_intelhad *intelhaddata)
 891 {
 892         struct snd_pcm_runtime *runtime = substream->runtime;
 893         int i, num_periods;
 894
 895         num_periods = runtime->periods;
 896         intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
 897         /* set the minimum 2 BDs for num_periods=1 */
 898         intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
 899         intelhaddata->period_bytes =
 900                 frames_to_bytes(runtime, runtime->period_size);
 901         WARN_ON(intelhaddata->period_bytes & 0x3f);
 902
 903         intelhaddata->bd_head = 0;
 904         intelhaddata->pcmbuf_head = 0;
 905         intelhaddata->pcmbuf_filled = 0;
 906
 907         for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
 908                 if (i < intelhaddata->num_bds)
 909                         had_prog_bd(substream, intelhaddata);
 910                 else /* invalidate the rest */
 911                         had_invalidate_bd(intelhaddata, i);
 912         }
 913
 914         intelhaddata->bd_head = 0; /* reset at head again before starting */
 915 }
 916
 917 /* process a bd, advance to the next */
 918 static void had_advance_ringbuf(struct snd_pcm_substream *substream,
 919                                 struct snd_intelhad *intelhaddata)
 920 {
 921         int num_periods = substream->runtime->periods;
 922
 923         /* reprogram the next buffer */
 924         had_prog_bd(substream, intelhaddata);
 925
 926         /* proceed to next */
 927         intelhaddata->pcmbuf_head++;
 928         intelhaddata->pcmbuf_head %= num_periods;
 929 }
 930
 931 /* process the current BD(s);
 932  * returns the current PCM buffer byte position, or -EPIPE for underrun.
 933  */
 934 static int had_process_ringbuf(struct snd_pcm_substream *substream,
 935                                struct snd_intelhad *intelhaddata)
 936 {
 937         int len, processed;
 938         unsigned long flags;
 939
 940         processed = 0;
 941         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 942         for (;;) {
 943                 /* get the remaining bytes on the buffer */
 944                 had_read_register(intelhaddata,
 945                                   AUD_BUF_LEN(intelhaddata->bd_head),
 946                                   &len);
 947                 if (len < 0 || len > intelhaddata->period_bytes) {
 948                         dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
 949                                 len);
 950                         len = -EPIPE;
 951                         goto out;
 952                 }
 953
 954                 if (len > 0) /* OK, this is the current buffer */
 955                         break;
 956
 957                 /* len=0 => already empty, check the next buffer */
 958                 if (++processed >= intelhaddata->num_bds) {
 959                         len = -EPIPE; /* all empty? - report underrun */
 960                         goto out;
 961                 }
 962                 had_advance_ringbuf(substream, intelhaddata);
 963         }
 964
 965         len = intelhaddata->period_bytes - len;
 966         len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
 967  out:
 968         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 969         return len;
 970 }
 971
 972 /* called from irq handler */
 973 static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
 974 {
 975         struct snd_pcm_substream *substream;
 976
 977         substream = had_substream_get(intelhaddata);
 978         if (!substream)
 979                 return; /* no stream? - bail out */
 980
 981         if (!intelhaddata->connected) {
 982                 snd_pcm_stop_xrun(substream);
 983                 goto out; /* disconnected? - bail out */
 984         }
 985
 986         /* process or stop the stream */
 987         if (had_process_ringbuf(substream, intelhaddata) < 0)
 988                 snd_pcm_stop_xrun(substream);
 989         else
 990                 snd_pcm_period_elapsed(substream);
 991
 992  out:
 993         had_substream_put(intelhaddata);
 994 }
 995
 996 /*
 997  * The interrupt status 'sticky' bits might not be cleared by
 998  * setting '1' to that bit once...
 999  */
1000 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
1001 {
1002         int i;
1003         u32 val;
1004
1005         for (i = 0; i < 100; i++) {
1006                 /* clear bit30, 31 AUD_HDMI_STATUS */
1007                 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
1008                 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
1009                         return;
1010                 udelay(100);
1011                 cond_resched();
1012                 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
1013         }
1014         dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
1015 }
1016
1017 /* Perform some reset procedure but only when need_reset is set;
1018  * this is called from prepare or hw_free callbacks once after trigger STOP
1019  * or underrun has been processed in order to settle down the h/w state.
1020  */
1021 static void had_do_reset(struct snd_intelhad *intelhaddata)
1022 {
1023         if (!intelhaddata->need_reset || !intelhaddata->connected)
1024                 return;
1025
1026         /* Reset buffer pointers */
1027         had_reset_audio(intelhaddata);
1028         wait_clear_underrun_bit(intelhaddata);
1029         intelhaddata->need_reset = false;
1030 }
1031
1032 /* called from irq handler */
1033 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1034 {
1035         struct snd_pcm_substream *substream;
1036
1037         /* Report UNDERRUN error to above layers */
1038         substream = had_substream_get(intelhaddata);
1039         if (substream) {
1040                 snd_pcm_stop_xrun(substream);
1041                 had_substream_put(intelhaddata);
1042         }
1043         intelhaddata->need_reset = true;
1044 }
1045
1046 /*
1047  * ALSA PCM open callback
1048  */
1049 static int had_pcm_open(struct snd_pcm_substream *substream)
1050 {
1051         struct snd_intelhad *intelhaddata;
1052         struct snd_pcm_runtime *runtime;
1053         int retval;
1054
1055         intelhaddata = snd_pcm_substream_chip(substream);
1056         runtime = substream->runtime;
1057
1058         pm_runtime_get_sync(intelhaddata->dev);
1059
1060         /* set the runtime hw parameter with local snd_pcm_hardware struct */
1061         runtime->hw = had_pcm_hardware;
1062
1063         retval = snd_pcm_hw_constraint_integer(runtime,
1064                          SNDRV_PCM_HW_PARAM_PERIODS);
1065         if (retval < 0)
1066                 goto error;
1067
1068         /* Make sure, that the period size is always aligned
1069          * 64byte boundary
1070          */
1071         retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1072                         SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1073         if (retval < 0)
1074                 goto error;
1075
1076         retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1077         if (retval < 0)
1078                 goto error;
1079
1080         /* expose PCM substream */
1081         spin_lock_irq(&intelhaddata->had_spinlock);
1082         intelhaddata->stream_info.substream = substream;
1083         intelhaddata->stream_info.substream_refcount++;
1084         spin_unlock_irq(&intelhaddata->had_spinlock);
1085
1086         return retval;
1087  error:
1088         pm_runtime_mark_last_busy(intelhaddata->dev);
1089         pm_runtime_put_autosuspend(intelhaddata->dev);
1090         return retval;
1091 }
1092
1093 /*
1094  * ALSA PCM close callback
1095  */
1096 static int had_pcm_close(struct snd_pcm_substream *substream)
1097 {
1098         struct snd_intelhad *intelhaddata;
1099
1100         intelhaddata = snd_pcm_substream_chip(substream);
1101
1102         /* unreference and sync with the pending PCM accesses */
1103         spin_lock_irq(&intelhaddata->had_spinlock);
1104         intelhaddata->stream_info.substream = NULL;
1105         intelhaddata->stream_info.substream_refcount--;
1106         while (intelhaddata->stream_info.substream_refcount > 0) {
1107                 spin_unlock_irq(&intelhaddata->had_spinlock);
1108                 cpu_relax();
1109                 spin_lock_irq(&intelhaddata->had_spinlock);
1110         }
1111         spin_unlock_irq(&intelhaddata->had_spinlock);
1112
1113         pm_runtime_mark_last_busy(intelhaddata->dev);
1114         pm_runtime_put_autosuspend(intelhaddata->dev);
1115         return 0;
1116 }
1117
1118 /*
1119  * ALSA PCM hw_params callback
1120  */
1121 static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1122                              struct snd_pcm_hw_params *hw_params)
1123 {
1124         struct snd_intelhad *intelhaddata;
1125         unsigned long addr;
1126         int pages, buf_size, retval;
1127
1128         intelhaddata = snd_pcm_substream_chip(substream);
1129         buf_size = params_buffer_bytes(hw_params);
1130         retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1131         if (retval < 0)
1132                 return retval;
1133         dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1134                 __func__, buf_size);
1135         /* mark the pages as uncached region */
1136         addr = (unsigned long) substream->runtime->dma_area;
1137         pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1138         retval = set_memory_uc(addr, pages);
1139         if (retval) {
1140                 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1141                         retval);
1142                 return retval;
1143         }
1144         memset(substream->runtime->dma_area, 0, buf_size);
1145
1146         return retval;
1147 }
1148
1149 /*
1150  * ALSA PCM hw_free callback
1151  */
1152 static int had_pcm_hw_free(struct snd_pcm_substream *substream)
1153 {
1154         struct snd_intelhad *intelhaddata;
1155         unsigned long addr;
1156         u32 pages;
1157
1158         intelhaddata = snd_pcm_substream_chip(substream);
1159         had_do_reset(intelhaddata);
1160
1161         /* mark back the pages as cached/writeback region before the free */
1162         if (substream->runtime->dma_area != NULL) {
1163                 addr = (unsigned long) substream->runtime->dma_area;
1164                 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1165                                                                 PAGE_SIZE;
1166                 set_memory_wb(addr, pages);
1167                 return snd_pcm_lib_free_pages(substream);
1168         }
1169         return 0;
1170 }
1171
1172 /*
1173  * ALSA PCM trigger callback
1174  */
1175 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1176 {
1177         int retval = 0;
1178         struct snd_intelhad *intelhaddata;
1179
1180         intelhaddata = snd_pcm_substream_chip(substream);
1181
1182         spin_lock(&intelhaddata->had_spinlock);
1183         switch (cmd) {
1184         case SNDRV_PCM_TRIGGER_START:
1185         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1186         case SNDRV_PCM_TRIGGER_RESUME:
1187                 /* Enable Audio */
1188                 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
1189                 had_enable_audio(intelhaddata, true);
1190                 break;
1191
1192         case SNDRV_PCM_TRIGGER_STOP:
1193         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1194                 /* Disable Audio */
1195                 had_enable_audio(intelhaddata, false);
1196                 intelhaddata->need_reset = true;
1197                 break;
1198
1199         default:
1200                 retval = -EINVAL;
1201         }
1202         spin_unlock(&intelhaddata->had_spinlock);
1203         return retval;
1204 }
1205
1206 /*
1207  * ALSA PCM prepare callback
1208  */
1209 static int had_pcm_prepare(struct snd_pcm_substream *substream)
1210 {
1211         int retval;
1212         u32 disp_samp_freq, n_param;
1213         u32 link_rate = 0;
1214         struct snd_intelhad *intelhaddata;
1215         struct snd_pcm_runtime *runtime;
1216
1217         intelhaddata = snd_pcm_substream_chip(substream);
1218         runtime = substream->runtime;
1219
1220         dev_dbg(intelhaddata->dev, "period_size=%d\n",
1221                 (int)frames_to_bytes(runtime, runtime->period_size));
1222         dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1223         dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1224                 (int)snd_pcm_lib_buffer_bytes(substream));
1225         dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1226         dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1227
1228         had_do_reset(intelhaddata);
1229
1230         /* Get N value in KHz */
1231         disp_samp_freq = intelhaddata->tmds_clock_speed;
1232
1233         retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1234         if (retval) {
1235                 dev_err(intelhaddata->dev,
1236                         "programming N value failed %#x\n", retval);
1237                 goto prep_end;
1238         }
1239
1240         if (intelhaddata->dp_output)
1241                 link_rate = intelhaddata->link_rate;
1242
1243         had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1244                      n_param, intelhaddata);
1245
1246         had_prog_dip(substream, intelhaddata);
1247
1248         retval = had_init_audio_ctrl(substream, intelhaddata);
1249
1250         /* Prog buffer address */
1251         had_init_ringbuf(substream, intelhaddata);
1252
1253         /*
1254          * Program channel mapping in following order:
1255          * FL, FR, C, LFE, RL, RR
1256          */
1257
1258         had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1259
1260 prep_end:
1261         return retval;
1262 }
1263
1264 /*
1265  * ALSA PCM pointer callback
1266  */
1267 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1268 {
1269         struct snd_intelhad *intelhaddata;
1270         int len;
1271
1272         intelhaddata = snd_pcm_substream_chip(substream);
1273
1274         if (!intelhaddata->connected)
1275                 return SNDRV_PCM_POS_XRUN;
1276
1277         len = had_process_ringbuf(substream, intelhaddata);
1278         if (len < 0)
1279                 return SNDRV_PCM_POS_XRUN;
1280         len = bytes_to_frames(substream->runtime, len);
1281         /* wrapping may happen when periods=1 */
1282         len %= substream->runtime->buffer_size;
1283         return len;
1284 }
1285
1286 /*
1287  * ALSA PCM mmap callback
1288  */
1289 static int had_pcm_mmap(struct snd_pcm_substream *substream,
1290                         struct vm_area_struct *vma)
1291 {
1292         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1293         return remap_pfn_range(vma, vma->vm_start,
1294                         substream->dma_buffer.addr >> PAGE_SHIFT,
1295                         vma->vm_end - vma->vm_start, vma->vm_page_prot);
1296 }
1297
1298 /*
1299  * ALSA PCM ops
1300  */
1301 static const struct snd_pcm_ops had_pcm_ops = {
1302         .open =         had_pcm_open,
1303         .close =        had_pcm_close,
1304         .ioctl =        snd_pcm_lib_ioctl,
1305         .hw_params =    had_pcm_hw_params,
1306         .hw_free =      had_pcm_hw_free,
1307         .prepare =      had_pcm_prepare,
1308         .trigger =      had_pcm_trigger,
1309         .pointer =      had_pcm_pointer,
1310         .mmap =         had_pcm_mmap,
1311 };
1312
1313 /* process mode change of the running stream; called in mutex */
1314 static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1315 {
1316         struct snd_pcm_substream *substream;
1317         int retval = 0;
1318         u32 disp_samp_freq, n_param;
1319         u32 link_rate = 0;
1320
1321         substream = had_substream_get(intelhaddata);
1322         if (!substream)
1323                 return 0;
1324
1325         /* Disable Audio */
1326         had_enable_audio(intelhaddata, false);
1327
1328         /* Update CTS value */
1329         disp_samp_freq = intelhaddata->tmds_clock_speed;
1330
1331         retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1332         if (retval) {
1333                 dev_err(intelhaddata->dev,
1334                         "programming N value failed %#x\n", retval);
1335                 goto out;
1336         }
1337
1338         if (intelhaddata->dp_output)
1339                 link_rate = intelhaddata->link_rate;
1340
1341         had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1342                      n_param, intelhaddata);
1343
1344         /* Enable Audio */
1345         had_enable_audio(intelhaddata, true);
1346
1347 out:
1348         had_substream_put(intelhaddata);
1349         return retval;
1350 }
1351
1352 /* process hot plug, called from wq with mutex locked */
1353 static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1354 {
1355         struct snd_pcm_substream *substream;
1356
1357         spin_lock_irq(&intelhaddata->had_spinlock);
1358         if (intelhaddata->connected) {
1359                 dev_dbg(intelhaddata->dev, "Device already connected\n");
1360                 spin_unlock_irq(&intelhaddata->had_spinlock);
1361                 return;
1362         }
1363
1364         intelhaddata->connected = true;
1365         dev_dbg(intelhaddata->dev,
1366                 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1367                         __func__, __LINE__);
1368         spin_unlock_irq(&intelhaddata->had_spinlock);
1369
1370         had_build_channel_allocation_map(intelhaddata);
1371
1372         /* Report to above ALSA layer */
1373         substream = had_substream_get(intelhaddata);
1374         if (substream) {
1375                 snd_pcm_stop_xrun(substream);
1376                 had_substream_put(intelhaddata);
1377         }
1378
1379         snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
1380 }
1381
1382 /* process hot unplug, called from wq with mutex locked */
1383 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1384 {
1385         struct snd_pcm_substream *substream;
1386
1387         spin_lock_irq(&intelhaddata->had_spinlock);
1388         if (!intelhaddata->connected) {
1389                 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1390                 spin_unlock_irq(&intelhaddata->had_spinlock);
1391                 return;
1392
1393         }
1394
1395         /* Disable Audio */
1396         had_enable_audio(intelhaddata, false);
1397
1398         intelhaddata->connected = false;
1399         dev_dbg(intelhaddata->dev,
1400                 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1401                         __func__, __LINE__);
1402         spin_unlock_irq(&intelhaddata->had_spinlock);
1403
1404         kfree(intelhaddata->chmap->chmap);
1405         intelhaddata->chmap->chmap = NULL;
1406
1407         /* Report to above ALSA layer */
1408         substream = had_substream_get(intelhaddata);
1409         if (substream) {
1410                 snd_pcm_stop_xrun(substream);
1411                 had_substream_put(intelhaddata);
1412         }
1413
1414         snd_jack_report(intelhaddata->jack, 0);
1415 }
1416
1417 /*
1418  * ALSA iec958 and ELD controls
1419  */
1420
1421 static int had_iec958_info(struct snd_kcontrol *kcontrol,
1422                                 struct snd_ctl_elem_info *uinfo)
1423 {
1424         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1425         uinfo->count = 1;
1426         return 0;
1427 }
1428
1429 static int had_iec958_get(struct snd_kcontrol *kcontrol,
1430                                 struct snd_ctl_elem_value *ucontrol)
1431 {
1432         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1433
1434         mutex_lock(&intelhaddata->mutex);
1435         ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1436         ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1437         ucontrol->value.iec958.status[2] =
1438                                         (intelhaddata->aes_bits >> 16) & 0xff;
1439         ucontrol->value.iec958.status[3] =
1440                                         (intelhaddata->aes_bits >> 24) & 0xff;
1441         mutex_unlock(&intelhaddata->mutex);
1442         return 0;
1443 }
1444
1445 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1446                                 struct snd_ctl_elem_value *ucontrol)
1447 {
1448         ucontrol->value.iec958.status[0] = 0xff;
1449         ucontrol->value.iec958.status[1] = 0xff;
1450         ucontrol->value.iec958.status[2] = 0xff;
1451         ucontrol->value.iec958.status[3] = 0xff;
1452         return 0;
1453 }
1454
1455 static int had_iec958_put(struct snd_kcontrol *kcontrol,
1456                                 struct snd_ctl_elem_value *ucontrol)
1457 {
1458         unsigned int val;
1459         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1460         int changed = 0;
1461
1462         val = (ucontrol->value.iec958.status[0] << 0) |
1463                 (ucontrol->value.iec958.status[1] << 8) |
1464                 (ucontrol->value.iec958.status[2] << 16) |
1465                 (ucontrol->value.iec958.status[3] << 24);
1466         mutex_lock(&intelhaddata->mutex);
1467         if (intelhaddata->aes_bits != val) {
1468                 intelhaddata->aes_bits = val;
1469                 changed = 1;
1470         }
1471         mutex_unlock(&intelhaddata->mutex);
1472         return changed;
1473 }
1474
1475 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1476                             struct snd_ctl_elem_info *uinfo)
1477 {
1478         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1479         uinfo->count = HDMI_MAX_ELD_BYTES;
1480         return 0;
1481 }
1482
1483 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1484                            struct snd_ctl_elem_value *ucontrol)
1485 {
1486         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1487
1488         mutex_lock(&intelhaddata->mutex);
1489         memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1490                HDMI_MAX_ELD_BYTES);
1491         mutex_unlock(&intelhaddata->mutex);
1492         return 0;
1493 }
1494
1495 static const struct snd_kcontrol_new had_controls[] = {
1496         {
1497                 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1498                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1499                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1500                 .info = had_iec958_info, /* shared */
1501                 .get = had_iec958_mask_get,
1502         },
1503         {
1504                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1505                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1506                 .info = had_iec958_info,
1507                 .get = had_iec958_get,
1508                 .put = had_iec958_put,
1509         },
1510         {
1511                 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1512                            SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1513                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1514                 .name = "ELD",
1515                 .info = had_ctl_eld_info,
1516                 .get = had_ctl_eld_get,
1517         },
1518 };
1519
1520 /*
1521  * audio interrupt handler
1522  */
1523 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1524 {
1525         struct snd_intelhad_card *card_ctx = dev_id;
1526         int port;
1527
1528         for_each_port(card_ctx, port) {
1529                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1530                 u32 audio_stat;
1531
1532                 /* use raw register access to ack IRQs even while disconnected */
1533                 audio_stat = had_read_register_raw(ctx, AUD_HDMI_STATUS);
1534
1535                 if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1536                         had_write_register_raw(ctx, AUD_HDMI_STATUS,
1537                                                HDMI_AUDIO_UNDERRUN);
1538                         had_process_buffer_underrun(ctx);
1539                 }
1540
1541                 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1542                         had_write_register_raw(ctx, AUD_HDMI_STATUS,
1543                                                HDMI_AUDIO_BUFFER_DONE);
1544                         had_process_buffer_done(ctx);
1545                 }
1546         }
1547
1548         return IRQ_HANDLED;
1549 }
1550
1551 /*
1552  * monitor plug/unplug notification from i915; just kick off the work
1553  */
1554 static void notify_audio_lpe(struct platform_device *pdev)
1555 {
1556         struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1557         int port;
1558
1559         for_each_port(card_ctx, port) {
1560                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1561
1562                 schedule_work(&ctx->hdmi_audio_wq);
1563         }
1564 }
1565
1566 /* the work to handle monitor hot plug/unplug */
1567 static void had_audio_wq(struct work_struct *work)
1568 {
1569         struct snd_intelhad *ctx =
1570                 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1571         struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1572         struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port;
1573
1574         pm_runtime_get_sync(ctx->dev);
1575         mutex_lock(&ctx->mutex);
1576         if (ppdata->pipe < 0) {
1577                 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1578                         __func__);
1579                 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
1580                 had_process_hot_unplug(ctx);
1581         } else {
1582                 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1583                         __func__, ppdata->port, ppdata->ls_clock);
1584
1585                 switch (ppdata->pipe) {
1586                 case 0:
1587                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1588                         break;
1589                 case 1:
1590                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1591                         break;
1592                 case 2:
1593                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1594                         break;
1595                 default:
1596                         dev_dbg(ctx->dev, "Invalid pipe %d\n",
1597                                 ppdata->pipe);
1598                         break;
1599                 }
1600
1601                 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld));
1602
1603                 ctx->dp_output = ppdata->dp_output;
1604                 if (ctx->dp_output) {
1605                         ctx->tmds_clock_speed = 0;
1606                         ctx->link_rate = ppdata->ls_clock;
1607                 } else {
1608                         ctx->tmds_clock_speed = ppdata->ls_clock;
1609                         ctx->link_rate = 0;
1610                 }
1611
1612                 had_process_hot_plug(ctx);
1613
1614                 /* Process mode change if stream is active */
1615                 had_process_mode_change(ctx);
1616         }
1617         mutex_unlock(&ctx->mutex);
1618         pm_runtime_mark_last_busy(ctx->dev);
1619         pm_runtime_put_autosuspend(ctx->dev);
1620 }
1621
1622 /*
1623  * Jack interface
1624  */
1625 static int had_create_jack(struct snd_intelhad *ctx,
1626                            struct snd_pcm *pcm)
1627 {
1628         char hdmi_str[32];
1629         int err;
1630
1631         snprintf(hdmi_str, sizeof(hdmi_str),
1632                  "HDMI/DP,pcm=%d", pcm->device);
1633
1634         err = snd_jack_new(ctx->card_ctx->card, hdmi_str,
1635                            SND_JACK_AVOUT, &ctx->jack,
1636                            true, false);
1637         if (err < 0)
1638                 return err;
1639         ctx->jack->private_data = ctx;
1640         return 0;
1641 }
1642
1643 /*
1644  * PM callbacks
1645  */
1646
1647 static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
1648 {
1649         struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1650         int port;
1651
1652         for_each_port(card_ctx, port) {
1653                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1654                 struct snd_pcm_substream *substream;
1655
1656                 substream = had_substream_get(ctx);
1657                 if (substream) {
1658                         snd_pcm_suspend(substream);
1659                         had_substream_put(ctx);
1660                 }
1661         }
1662
1663         return 0;
1664 }
1665
1666 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
1667 {
1668         struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1669         int err;
1670
1671         err = hdmi_lpe_audio_runtime_suspend(dev);
1672         if (!err)
1673                 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot);
1674         return err;
1675 }
1676
1677 static int hdmi_lpe_audio_runtime_resume(struct device *dev)
1678 {
1679         pm_runtime_mark_last_busy(dev);
1680         return 0;
1681 }
1682
1683 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
1684 {
1685         struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1686
1687         hdmi_lpe_audio_runtime_resume(dev);
1688         snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0);
1689         return 0;
1690 }
1691
1692 /* release resources */
1693 static void hdmi_lpe_audio_free(struct snd_card *card)
1694 {
1695         struct snd_intelhad_card *card_ctx = card->private_data;
1696         struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data;
1697         int port;
1698
1699         spin_lock_irq(&pdata->lpe_audio_slock);
1700         pdata->notify_audio_lpe = NULL;
1701         spin_unlock_irq(&pdata->lpe_audio_slock);
1702
1703         for_each_port(card_ctx, port) {
1704                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1705
1706                 cancel_work_sync(&ctx->hdmi_audio_wq);
1707         }
1708
1709         if (card_ctx->mmio_start)
1710                 iounmap(card_ctx->mmio_start);
1711         if (card_ctx->irq >= 0)
1712                 free_irq(card_ctx->irq, card_ctx);
1713 }
1714
1715 /*
1716  * hdmi_lpe_audio_probe - start bridge with i915
1717  *
1718  * This function is called when the i915 driver creates the
1719  * hdmi-lpe-audio platform device.
1720  */
1721 static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1722 {
1723         struct snd_card *card;
1724         struct snd_intelhad_card *card_ctx;
1725         struct snd_pcm *pcm;
1726         struct intel_hdmi_lpe_audio_pdata *pdata;
1727         int irq;
1728         struct resource *res_mmio;
1729         int port, ret;
1730
1731         pdata = pdev->dev.platform_data;
1732         if (!pdata) {
1733                 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1734                 return -EINVAL;
1735         }
1736
1737         /* get resources */
1738         irq = platform_get_irq(pdev, 0);
1739         if (irq < 0) {
1740                 dev_err(&pdev->dev, "Could not get irq resource\n");
1741                 return -ENODEV;
1742         }
1743
1744         res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1745         if (!res_mmio) {
1746                 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1747                 return -ENXIO;
1748         }
1749
1750         /* create a card instance with ALSA framework */
1751         ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1752                            THIS_MODULE, sizeof(*card_ctx), &card);
1753         if (ret)
1754                 return ret;
1755
1756         card_ctx = card->private_data;
1757         card_ctx->dev = &pdev->dev;
1758         card_ctx->card = card;
1759         strcpy(card->driver, INTEL_HAD);
1760         strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1761         strcpy(card->longname, "Intel HDMI/DP LPE Audio");
1762
1763         card_ctx->irq = -1;
1764
1765         card->private_free = hdmi_lpe_audio_free;
1766
1767         platform_set_drvdata(pdev, card_ctx);
1768
1769         dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1770                 __func__, (unsigned int)res_mmio->start,
1771                 (unsigned int)res_mmio->end);
1772
1773         card_ctx->mmio_start = ioremap_nocache(res_mmio->start,
1774                                                (size_t)(resource_size(res_mmio)));
1775         if (!card_ctx->mmio_start) {
1776                 dev_err(&pdev->dev, "Could not get ioremap\n");
1777                 ret = -EACCES;
1778                 goto err;
1779         }
1780
1781         /* setup interrupt handler */
1782         ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1783                           pdev->name, card_ctx);
1784         if (ret < 0) {
1785                 dev_err(&pdev->dev, "request_irq failed\n");
1786                 goto err;
1787         }
1788
1789         card_ctx->irq = irq;
1790
1791         /* only 32bit addressable */
1792         dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1793         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1794
1795         init_channel_allocations();
1796
1797         card_ctx->num_ports = 1;
1798
1799         for_each_port(card_ctx, port) {
1800                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1801                 int i;
1802
1803                 ctx->card_ctx = card_ctx;
1804                 ctx->dev = card_ctx->dev;
1805
1806                 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1807
1808                 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1809
1810                 ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
1811                                   MAX_CAP_STREAMS, &pcm);
1812                 if (ret)
1813                         goto err;
1814
1815                 /* setup private data which can be retrieved when required */
1816                 pcm->private_data = ctx;
1817                 pcm->info_flags = 0;
1818                 strncpy(pcm->name, card->shortname, strlen(card->shortname));
1819                 /* setup the ops for playabck */
1820                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1821
1822                 /* allocate dma pages;
1823                  * try to allocate 600k buffer as default which is large enough
1824                  */
1825                 snd_pcm_lib_preallocate_pages_for_all(pcm,
1826                                                       SNDRV_DMA_TYPE_DEV, NULL,
1827                                                       HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER);
1828
1829                 /* create controls */
1830                 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1831                         struct snd_kcontrol *kctl;
1832
1833                         kctl = snd_ctl_new1(&had_controls[i], ctx);
1834                         if (!kctl) {
1835                                 ret = -ENOMEM;
1836                                 goto err;
1837                         }
1838
1839                         kctl->id.device = pcm->device;
1840
1841                         ret = snd_ctl_add(card, kctl);
1842                         if (ret < 0)
1843                                 goto err;
1844                 }
1845
1846                 /* Register channel map controls */
1847                 ret = had_register_chmap_ctls(ctx, pcm);
1848                 if (ret < 0)
1849                         goto err;
1850
1851                 ret = had_create_jack(ctx, pcm);
1852                 if (ret < 0)
1853                         goto err;
1854         }
1855
1856         ret = snd_card_register(card);
1857         if (ret)
1858                 goto err;
1859
1860         spin_lock_irq(&pdata->lpe_audio_slock);
1861         pdata->notify_audio_lpe = notify_audio_lpe;
1862         spin_unlock_irq(&pdata->lpe_audio_slock);
1863
1864         pm_runtime_use_autosuspend(&pdev->dev);
1865         pm_runtime_mark_last_busy(&pdev->dev);
1866         pm_runtime_set_active(&pdev->dev);
1867
1868         dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1869         for_each_port(card_ctx, port) {
1870                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1871
1872                 schedule_work(&ctx->hdmi_audio_wq);
1873         }
1874
1875         return 0;
1876
1877 err:
1878         snd_card_free(card);
1879         return ret;
1880 }
1881
1882 /*
1883  * hdmi_lpe_audio_remove - stop bridge with i915
1884  *
1885  * This function is called when the platform device is destroyed.
1886  */
1887 static int hdmi_lpe_audio_remove(struct platform_device *pdev)
1888 {
1889         struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1890
1891         snd_card_free(card_ctx->card);
1892         return 0;
1893 }
1894
1895 static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1896         SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1897         SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend,
1898                            hdmi_lpe_audio_runtime_resume, NULL)
1899 };
1900
1901 static struct platform_driver hdmi_lpe_audio_driver = {
1902         .driver         = {
1903                 .name  = "hdmi-lpe-audio",
1904                 .pm = &hdmi_lpe_audio_pm,
1905         },
1906         .probe          = hdmi_lpe_audio_probe,
1907         .remove         = hdmi_lpe_audio_remove,
1908 };
1909
1910 module_platform_driver(hdmi_lpe_audio_driver);
1911 MODULE_ALIAS("platform:hdmi_lpe_audio");
1912
1913 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1914 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1915 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1916 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1917 MODULE_DESCRIPTION("Intel HDMI Audio driver");
1918 MODULE_LICENSE("GPL v2");
1919 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");