6 perf-list - List all symbolic event types
11 'perf list' [hw|sw|cache|tracepoint|event_glob]
15 This command displays the symbolic event types which can be selected in the
16 various perf commands with the -e option.
22 Events can optionally have a modifer by appending a colon and one or
23 more modifiers. Modifiers allow the user to restrict the events to be
24 counted. The following modifiers exist:
26 u - user-space counting
28 h - hypervisor counting
29 G - guest counting (in KVM guests)
30 H - host counting (not in KVM guests)
33 The 'p' modifier can be used for specifying how precise the instruction
34 address should be. The 'p' modifier can be specified multiple times:
36 0 - SAMPLE_IP can have arbitrary skid
37 1 - SAMPLE_IP must have constant skid
38 2 - SAMPLE_IP requested to have 0 skid
39 3 - SAMPLE_IP must have 0 skid
41 For Intel systems precise event sampling is implemented with PEBS
42 which supports up to precise-level 2.
44 On AMD systems it is implemented using IBS (up to precise-level 2).
45 The precise modifier works with event types 0x76 (cpu-cycles, CPU
46 clocks not halted) and 0xC1 (micro-ops retired). Both events map to
47 IBS execution sampling (IBS op) with the IBS Op Counter Control bit
48 (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
49 Manual Volume 2: System Programming, 13.3 Instruction-Based
50 Sampling). Examples to use IBS:
52 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
53 perf record -a -e r076:p ... # same as -e cpu-cycles:p
54 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
56 RAW HARDWARE EVENT DESCRIPTOR
57 -----------------------------
58 Even when an event is not available in a symbolic form within perf right now,
59 it can be encoded in a per processor specific way.
61 For instance For x86 CPUs NNN represents the raw register encoding with the
62 layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
63 of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
64 Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
66 Note: Only the following bit fields can be set in x86 counter
67 registers: event, umask, edge, inv, cmask. Esp. guest/host only and
68 OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
73 If the Intel docs for a QM720 Core i7 describe an event as:
75 Event Umask Event Mask
76 Num. Value Mnemonic Description Comment
78 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
79 delivered by loop stream detector invert to count
82 raw encoding of 0x1A8 can be used:
84 perf stat -e r1a8 -a sleep 1
85 perf record -e r1a8 ...
87 You should refer to the processor specific documentation for getting these
88 details. Some of them are referenced in the SEE ALSO section below.
93 Without options all known events will be listed.
95 To limit the list use:
97 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
99 . 'sw' or 'software' to list software events such as context switches, etc.
101 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
103 . 'tracepoint' to list all tracepoint events, alternatively use
104 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
107 . If none of the above is matched, it will apply the supplied glob to all
108 events, printing the ones that match.
110 One or more types can be used at the same time, listing the events for the
115 linkperf:perf-stat[1], linkperf:perf-top[1],
116 linkperf:perf-record[1],
117 http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
118 http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]