6 perf-list - List all symbolic event types
11 'perf list' [--no-desc] [--long-desc] [hw|sw|cache|tracepoint|pmu|sdt|event_glob]
15 This command displays the symbolic event types which can be selected in the
16 various perf commands with the -e option.
21 Don't print descriptions.
25 Print longer event descriptions.
28 Print how named events are resolved internally into perf events, and also
29 any extra expressions computed by perf stat.
36 Events can optionally have a modifier by appending a colon and one or
37 more modifiers. Modifiers allow the user to restrict the events to be
38 counted. The following modifiers exist:
40 u - user-space counting
42 h - hypervisor counting
44 G - guest counting (in KVM guests)
45 H - host counting (not in KVM guests)
47 P - use maximum detected precise level
48 S - read sample value (PERF_SAMPLE_READ)
49 D - pin the event to the PMU
51 The 'p' modifier can be used for specifying how precise the instruction
52 address should be. The 'p' modifier can be specified multiple times:
54 0 - SAMPLE_IP can have arbitrary skid
55 1 - SAMPLE_IP must have constant skid
56 2 - SAMPLE_IP requested to have 0 skid
57 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
58 sample shadowing effects.
60 For Intel systems precise event sampling is implemented with PEBS
61 which supports up to precise-level 2, and precise level 3 for
64 On AMD systems it is implemented using IBS (up to precise-level 2).
65 The precise modifier works with event types 0x76 (cpu-cycles, CPU
66 clocks not halted) and 0xC1 (micro-ops retired). Both events map to
67 IBS execution sampling (IBS op) with the IBS Op Counter Control bit
68 (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
69 Manual Volume 2: System Programming, 13.3 Instruction-Based
70 Sampling). Examples to use IBS:
72 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
73 perf record -a -e r076:p ... # same as -e cpu-cycles:p
74 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
76 RAW HARDWARE EVENT DESCRIPTOR
77 -----------------------------
78 Even when an event is not available in a symbolic form within perf right now,
79 it can be encoded in a per processor specific way.
81 For instance For x86 CPUs NNN represents the raw register encoding with the
82 layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
83 of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
84 Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
86 Note: Only the following bit fields can be set in x86 counter
87 registers: event, umask, edge, inv, cmask. Esp. guest/host only and
88 OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
93 If the Intel docs for a QM720 Core i7 describe an event as:
95 Event Umask Event Mask
96 Num. Value Mnemonic Description Comment
98 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
99 delivered by loop stream detector invert to count
102 raw encoding of 0x1A8 can be used:
104 perf stat -e r1a8 -a sleep 1
105 perf record -e r1a8 ...
107 You should refer to the processor specific documentation for getting these
108 details. Some of them are referenced in the SEE ALSO section below.
113 perf also supports an extended syntax for specifying raw parameters
114 to PMUs. Using this typically requires looking up the specific event
115 in the CPU vendor specific documentation.
117 The available PMUs and their raw parameters can be listed with
119 ls /sys/devices/*/format
121 For example the raw event "LSD.UOPS" core pmu event above could
124 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=1/ ...
129 Some PMUs are not associated with a core, but with a whole CPU socket.
130 Events on these PMUs generally cannot be sampled, but only counted globally
131 with perf stat -a. They can be bound to one logical CPU, but will measure
132 all the CPUs in the same socket.
134 This example measures memory bandwidth every second
135 on the first memory controller on socket 0 of a Intel Xeon system
137 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
139 Each memory controller has its own PMU. Measuring the complete system
140 bandwidth would require specifying all imc PMUs (see perf list output),
141 and adding the values together.
143 This example measures the combined core power every second
145 perf stat -I 1000 -e power/energy-cores/ -a
150 For non root users generally only context switched PMU events are available.
151 This is normally only the events in the cpu PMU, the predefined events
152 like cycles and instructions and some software events.
154 Other PMUs and global measurements are normally root only.
155 Some event qualifiers, such as "any", are also root only.
157 This can be overriden by setting the kernel.perf_event_paranoid
158 sysctl to -1, which allows non root to use these events.
160 For accessing trace point events perf needs to have read access to
161 /sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
167 Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
168 that allows low overhead execution tracing. These are described in a separate
169 intel-pt.txt document.
174 Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
177 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
179 This means that when provided as an event, a value for '?' must
180 also be supplied. For example:
182 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
187 Perf supports time based multiplexing of events, when the number of events
188 active exceeds the number of hardware performance counters. Multiplexing
189 can cause measurement errors when the workload changes its execution
192 When metrics are computed using formulas from event counts, it is useful to
193 ensure some events are always measured together as a group to minimize multiplexing
194 errors. Event groups can be specified using { }.
196 perf stat -e '{instructions,cycles}' ...
198 The number of available performance counters depend on the CPU. A group
199 cannot contain more events than available counters.
200 For example Intel Core CPUs typically have four generic performance counters
201 for the core, plus three fixed counters for instructions, cycles and
202 ref-cycles. Some special events have restrictions on which counter they
203 can schedule, and may not support multiple instances in a single group.
204 When too many events are specified in the group none of them will not
207 Globally pinned events can limit the number of counters available for
208 other groups. On x86 systems, the NMI watchdog pins a counter by default.
209 The nmi watchdog can be disabled as root with
211 echo 0 > /proc/sys/kernel/nmi_watchdog
213 Events from multiple different PMUs cannot be mixed in a group, with
214 some exceptions for software events.
219 perf also supports group leader sampling using the :S specifier.
221 perf record -e '{cycles,instructions}:S' ...
224 Normally all events in a event group sample, but with :S only
225 the first event (the leader) samples, and it only reads the values of the
226 other events in the group.
231 Without options all known events will be listed.
233 To limit the list use:
235 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
237 . 'sw' or 'software' to list software events such as context switches, etc.
239 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
241 . 'tracepoint' to list all tracepoint events, alternatively use
242 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
245 . 'pmu' to print the kernel supplied PMU events.
247 . 'sdt' to list all Statically Defined Tracepoint events.
249 . If none of the above is matched, it will apply the supplied glob to all
250 events, printing the ones that match.
252 . As a last resort, it will do a substring search in all event names.
254 One or more types can be used at the same time, listing the events for the
259 . '--raw-dump', shows the raw-dump of all the events.
260 . '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
261 a certain kind of events.
265 linkperf:perf-stat[1], linkperf:perf-top[1],
266 linkperf:perf-record[1],
267 http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
268 http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]