2 * Copyright (C) 2012-2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/compiler.h>
19 #include <linux/irqchip/arm-gic.h>
20 #include <linux/kvm_host.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/kvm_hyp.h>
25 static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
28 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
29 int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
34 expect_mi = !!(cpu_if->vgic_hcr & GICH_HCR_UIE);
36 for (i = 0; i < nr_lr; i++) {
37 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
40 expect_mi |= (!(cpu_if->vgic_lr[i] & GICH_LR_HW) &&
41 (cpu_if->vgic_lr[i] & GICH_LR_EOI));
45 cpu_if->vgic_misr = readl_relaxed(base + GICH_MISR);
47 if (cpu_if->vgic_misr & GICH_MISR_EOI) {
48 eisr0 = readl_relaxed(base + GICH_EISR0);
49 if (unlikely(nr_lr > 32))
50 eisr1 = readl_relaxed(base + GICH_EISR1);
57 cpu_if->vgic_misr = 0;
61 #ifdef CONFIG_CPU_BIG_ENDIAN
62 cpu_if->vgic_eisr = ((u64)eisr0 << 32) | eisr1;
64 cpu_if->vgic_eisr = ((u64)eisr1 << 32) | eisr0;
68 static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
70 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
71 int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
74 elrsr0 = readl_relaxed(base + GICH_ELRSR0);
75 if (unlikely(nr_lr > 32))
76 elrsr1 = readl_relaxed(base + GICH_ELRSR1);
80 #ifdef CONFIG_CPU_BIG_ENDIAN
81 cpu_if->vgic_elrsr = ((u64)elrsr0 << 32) | elrsr1;
83 cpu_if->vgic_elrsr = ((u64)elrsr1 << 32) | elrsr0;
87 static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
89 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
90 int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
93 for (i = 0; i < nr_lr; i++) {
94 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
97 if (cpu_if->vgic_elrsr & (1UL << i))
98 cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
100 cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
102 writel_relaxed(0, base + GICH_LR0 + (i * 4));
106 /* vcpu is already in the HYP VA space */
107 void __hyp_text __vgic_v2_save_state(struct kvm_vcpu *vcpu)
109 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
110 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
111 struct vgic_dist *vgic = &kvm->arch.vgic;
112 void __iomem *base = kern_hyp_va(vgic->vctrl_base);
117 cpu_if->vgic_vmcr = readl_relaxed(base + GICH_VMCR);
119 if (vcpu->arch.vgic_cpu.live_lrs) {
120 cpu_if->vgic_apr = readl_relaxed(base + GICH_APR);
122 save_maint_int_state(vcpu, base);
123 save_elrsr(vcpu, base);
124 save_lrs(vcpu, base);
126 writel_relaxed(0, base + GICH_HCR);
128 vcpu->arch.vgic_cpu.live_lrs = 0;
130 cpu_if->vgic_eisr = 0;
131 cpu_if->vgic_elrsr = ~0UL;
132 cpu_if->vgic_misr = 0;
133 cpu_if->vgic_apr = 0;
137 /* vcpu is already in the HYP VA space */
138 void __hyp_text __vgic_v2_restore_state(struct kvm_vcpu *vcpu)
140 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
141 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
142 struct vgic_dist *vgic = &kvm->arch.vgic;
143 void __iomem *base = kern_hyp_va(vgic->vctrl_base);
144 int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
152 for (i = 0; i < nr_lr; i++)
153 if (cpu_if->vgic_lr[i] & GICH_LR_STATE)
154 live_lrs |= 1UL << i;
157 writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
158 writel_relaxed(cpu_if->vgic_apr, base + GICH_APR);
159 for (i = 0; i < nr_lr; i++) {
160 if (!(live_lrs & (1UL << i)))
163 writel_relaxed(cpu_if->vgic_lr[i],
164 base + GICH_LR0 + (i * 4));
168 writel_relaxed(cpu_if->vgic_vmcr, base + GICH_VMCR);
169 vcpu->arch.vgic_cpu.live_lrs = live_lrs;
174 * __vgic_v2_perform_cpuif_access -- perform a GICV access on behalf of the
177 * @vcpu: the offending vcpu
180 * 1: GICV access successfully performed
181 * 0: Not a GICV access
182 * -1: Illegal GICV access
184 int __hyp_text __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu)
186 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
187 struct vgic_dist *vgic = &kvm->arch.vgic;
188 phys_addr_t fault_ipa;
192 /* Build the full address */
193 fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);
194 fault_ipa |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
196 /* If not for GICV, move on */
197 if (fault_ipa < vgic->vgic_cpu_base ||
198 fault_ipa >= (vgic->vgic_cpu_base + KVM_VGIC_V2_CPU_SIZE))
201 /* Reject anything but a 32bit access */
202 if (kvm_vcpu_dabt_get_as(vcpu) != sizeof(u32))
205 /* Not aligned? Don't bother */
209 rd = kvm_vcpu_dabt_get_rd(vcpu);
210 addr = kern_hyp_va((kern_hyp_va(&kvm_vgic_global_state))->vcpu_base_va);
211 addr += fault_ipa - vgic->vgic_cpu_base;
213 if (kvm_vcpu_dabt_iswrite(vcpu)) {
214 u32 data = vcpu_data_guest_to_host(vcpu,
215 vcpu_get_reg(vcpu, rd),
217 writel_relaxed(data, addr);
219 u32 data = readl_relaxed(addr);
220 vcpu_set_reg(vcpu, rd, vcpu_data_host_to_guest(vcpu, data,