virt/kvm/arm/hyp/vgic-v3-sr.c

   1 /*
   2  * Copyright (C) 2012-2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/compiler.h>
  19 #include <linux/irqchip/arm-gic-v3.h>
  20 #include <linux/kvm_host.h>
  21
  22 #include <asm/kvm_hyp.h>
  23
  24 #define vtr_to_max_lr_idx(v)            ((v) & 0xf)
  25 #define vtr_to_nr_pri_bits(v)           (((u32)(v) >> 29) + 1)
  26
  27 static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
  28 {
  29         switch (lr & 0xf) {
  30         case 0:
  31                 return read_gicreg(ICH_LR0_EL2);
  32         case 1:
  33                 return read_gicreg(ICH_LR1_EL2);
  34         case 2:
  35                 return read_gicreg(ICH_LR2_EL2);
  36         case 3:
  37                 return read_gicreg(ICH_LR3_EL2);
  38         case 4:
  39                 return read_gicreg(ICH_LR4_EL2);
  40         case 5:
  41                 return read_gicreg(ICH_LR5_EL2);
  42         case 6:
  43                 return read_gicreg(ICH_LR6_EL2);
  44         case 7:
  45                 return read_gicreg(ICH_LR7_EL2);
  46         case 8:
  47                 return read_gicreg(ICH_LR8_EL2);
  48         case 9:
  49                 return read_gicreg(ICH_LR9_EL2);
  50         case 10:
  51                 return read_gicreg(ICH_LR10_EL2);
  52         case 11:
  53                 return read_gicreg(ICH_LR11_EL2);
  54         case 12:
  55                 return read_gicreg(ICH_LR12_EL2);
  56         case 13:
  57                 return read_gicreg(ICH_LR13_EL2);
  58         case 14:
  59                 return read_gicreg(ICH_LR14_EL2);
  60         case 15:
  61                 return read_gicreg(ICH_LR15_EL2);
  62         }
  63
  64         unreachable();
  65 }
  66
  67 static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
  68 {
  69         switch (lr & 0xf) {
  70         case 0:
  71                 write_gicreg(val, ICH_LR0_EL2);
  72                 break;
  73         case 1:
  74                 write_gicreg(val, ICH_LR1_EL2);
  75                 break;
  76         case 2:
  77                 write_gicreg(val, ICH_LR2_EL2);
  78                 break;
  79         case 3:
  80                 write_gicreg(val, ICH_LR3_EL2);
  81                 break;
  82         case 4:
  83                 write_gicreg(val, ICH_LR4_EL2);
  84                 break;
  85         case 5:
  86                 write_gicreg(val, ICH_LR5_EL2);
  87                 break;
  88         case 6:
  89                 write_gicreg(val, ICH_LR6_EL2);
  90                 break;
  91         case 7:
  92                 write_gicreg(val, ICH_LR7_EL2);
  93                 break;
  94         case 8:
  95                 write_gicreg(val, ICH_LR8_EL2);
  96                 break;
  97         case 9:
  98                 write_gicreg(val, ICH_LR9_EL2);
  99                 break;
 100         case 10:
 101                 write_gicreg(val, ICH_LR10_EL2);
 102                 break;
 103         case 11:
 104                 write_gicreg(val, ICH_LR11_EL2);
 105                 break;
 106         case 12:
 107                 write_gicreg(val, ICH_LR12_EL2);
 108                 break;
 109         case 13:
 110                 write_gicreg(val, ICH_LR13_EL2);
 111                 break;
 112         case 14:
 113                 write_gicreg(val, ICH_LR14_EL2);
 114                 break;
 115         case 15:
 116                 write_gicreg(val, ICH_LR15_EL2);
 117                 break;
 118         }
 119 }
 120
 121 void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
 122 {
 123         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 124         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 125         u64 val;
 126
 127         /*
 128          * Make sure stores to the GIC via the memory mapped interface
 129          * are now visible to the system register interface.
 130          */
 131         if (!cpu_if->vgic_sre)
 132                 dsb(st);
 133
 134         if (used_lrs) {
 135                 int i;
 136                 u32 nr_pri_bits;
 137
 138                 cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
 139
 140                 write_gicreg(0, ICH_HCR_EL2);
 141                 val = read_gicreg(ICH_VTR_EL2);
 142                 nr_pri_bits = vtr_to_nr_pri_bits(val);
 143
 144                 for (i = 0; i <= used_lrs; i++) {
 145                         if (cpu_if->vgic_elrsr & (1 << i))
 146                                 cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
 147                         else
 148                                 cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
 149
 150                         __gic_v3_set_lr(0, i);
 151                 }
 152
 153                 switch (nr_pri_bits) {
 154                 case 7:
 155                         cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
 156                         cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
 157                 case 6:
 158                         cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
 159                 default:
 160                         cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
 161                 }
 162
 163                 switch (nr_pri_bits) {
 164                 case 7:
 165                         cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
 166                         cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
 167                 case 6:
 168                         cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
 169                 default:
 170                         cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
 171                 }
 172         } else {
 173                 cpu_if->vgic_elrsr = 0xffff;
 174                 cpu_if->vgic_ap0r[0] = 0;
 175                 cpu_if->vgic_ap0r[1] = 0;
 176                 cpu_if->vgic_ap0r[2] = 0;
 177                 cpu_if->vgic_ap0r[3] = 0;
 178                 cpu_if->vgic_ap1r[0] = 0;
 179                 cpu_if->vgic_ap1r[1] = 0;
 180                 cpu_if->vgic_ap1r[2] = 0;
 181                 cpu_if->vgic_ap1r[3] = 0;
 182         }
 183
 184         val = read_gicreg(ICC_SRE_EL2);
 185         write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
 186
 187         if (!cpu_if->vgic_sre) {
 188                 /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
 189                 isb();
 190                 write_gicreg(1, ICC_SRE_EL1);
 191         }
 192 }
 193
 194 void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
 195 {
 196         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 197         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 198         u64 val;
 199         u32 nr_pri_bits;
 200         int i;
 201
 202         /*
 203          * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
 204          * Group0 interrupt (as generated in GICv2 mode) to be
 205          * delivered as a FIQ to the guest, with potentially fatal
 206          * consequences. So we must make sure that ICC_SRE_EL1 has
 207          * been actually programmed with the value we want before
 208          * starting to mess with the rest of the GIC.
 209          */
 210         if (!cpu_if->vgic_sre) {
 211                 write_gicreg(0, ICC_SRE_EL1);
 212                 isb();
 213         }
 214
 215         val = read_gicreg(ICH_VTR_EL2);
 216         nr_pri_bits = vtr_to_nr_pri_bits(val);
 217
 218         if (used_lrs) {
 219                 write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
 220
 221                 switch (nr_pri_bits) {
 222                 case 7:
 223                         write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
 224                         write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
 225                 case 6:
 226                         write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
 227                 default:
 228                         write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
 229                 }
 230
 231                 switch (nr_pri_bits) {
 232                 case 7:
 233                         write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
 234                         write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
 235                 case 6:
 236                         write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
 237                 default:
 238                         write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
 239                 }
 240
 241                 for (i = 0; i < used_lrs; i++)
 242                         __gic_v3_set_lr(cpu_if->vgic_lr[i], i);
 243         }
 244
 245         /*
 246          * Ensures that the above will have reached the
 247          * (re)distributors. This ensure the guest will read the
 248          * correct values from the memory-mapped interface.
 249          */
 250         if (!cpu_if->vgic_sre) {
 251                 isb();
 252                 dsb(sy);
 253         }
 254
 255         /*
 256          * Prevent the guest from touching the GIC system registers if
 257          * SRE isn't enabled for GICv3 emulation.
 258          */
 259         write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
 260                      ICC_SRE_EL2);
 261 }
 262
 263 void __hyp_text __vgic_v3_init_lrs(void)
 264 {
 265         int max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
 266         int i;
 267
 268         for (i = 0; i <= max_lr_idx; i++)
 269                 __gic_v3_set_lr(0, i);
 270 }
 271
 272 u64 __hyp_text __vgic_v3_get_ich_vtr_el2(void)
 273 {
 274         return read_gicreg(ICH_VTR_EL2);
 275 }
 276
 277 u64 __hyp_text __vgic_v3_read_vmcr(void)
 278 {
 279         return read_gicreg(ICH_VMCR_EL2);
 280 }
 281
 282 void __hyp_text __vgic_v3_write_vmcr(u32 vmcr)
 283 {
 284         write_gicreg(vmcr, ICH_VMCR_EL2);
 285 }