virt/kvm/arm/vgic/vgic-mmio-v2.c

   1 /*
   2  * VGICv2 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <kvm/iodev.h>
  18 #include <kvm/arm_vgic.h>
  19
  20 #include "vgic.h"
  21 #include "vgic-mmio.h"
  22
  23 static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
  24                                             gpa_t addr, unsigned int len)
  25 {
  26         u32 value;
  27
  28         switch (addr & 0x0c) {
  29         case GIC_DIST_CTRL:
  30                 value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
  31                 break;
  32         case GIC_DIST_CTR:
  33                 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
  34                 value = (value >> 5) - 1;
  35                 value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
  36                 break;
  37         case GIC_DIST_IIDR:
  38                 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
  39                 break;
  40         default:
  41                 return 0;
  42         }
  43
  44         return value;
  45 }
  46
  47 static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
  48                                     gpa_t addr, unsigned int len,
  49                                     unsigned long val)
  50 {
  51         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
  52         bool was_enabled = dist->enabled;
  53
  54         switch (addr & 0x0c) {
  55         case GIC_DIST_CTRL:
  56                 dist->enabled = val & GICD_ENABLE;
  57                 if (!was_enabled && dist->enabled)
  58                         vgic_kick_vcpus(vcpu->kvm);
  59                 break;
  60         case GIC_DIST_CTR:
  61         case GIC_DIST_IIDR:
  62                 /* Nothing to do */
  63                 return;
  64         }
  65 }
  66
  67 static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
  68                                  gpa_t addr, unsigned int len,
  69                                  unsigned long val)
  70 {
  71         int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
  72         int intid = val & 0xf;
  73         int targets = (val >> 16) & 0xff;
  74         int mode = (val >> 24) & 0x03;
  75         int c;
  76         struct kvm_vcpu *vcpu;
  77
  78         switch (mode) {
  79         case 0x0:               /* as specified by targets */
  80                 break;
  81         case 0x1:
  82                 targets = (1U << nr_vcpus) - 1;                 /* all, ... */
  83                 targets &= ~(1U << source_vcpu->vcpu_id);       /* but self */
  84                 break;
  85         case 0x2:               /* this very vCPU only */
  86                 targets = (1U << source_vcpu->vcpu_id);
  87                 break;
  88         case 0x3:               /* reserved */
  89                 return;
  90         }
  91
  92         kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
  93                 struct vgic_irq *irq;
  94
  95                 if (!(targets & (1U << c)))
  96                         continue;
  97
  98                 irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
  99
 100                 spin_lock(&irq->irq_lock);
 101                 irq->pending_latch = true;
 102                 irq->source |= 1U << source_vcpu->vcpu_id;
 103
 104                 vgic_queue_irq_unlock(source_vcpu->kvm, irq);
 105                 vgic_put_irq(source_vcpu->kvm, irq);
 106         }
 107 }
 108
 109 static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
 110                                            gpa_t addr, unsigned int len)
 111 {
 112         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 113         int i;
 114         u64 val = 0;
 115
 116         for (i = 0; i < len; i++) {
 117                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 118
 119                 val |= (u64)irq->targets << (i * 8);
 120
 121                 vgic_put_irq(vcpu->kvm, irq);
 122         }
 123
 124         return val;
 125 }
 126
 127 static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
 128                                    gpa_t addr, unsigned int len,
 129                                    unsigned long val)
 130 {
 131         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 132         u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
 133         int i;
 134
 135         /* GICD_ITARGETSR[0-7] are read-only */
 136         if (intid < VGIC_NR_PRIVATE_IRQS)
 137                 return;
 138
 139         for (i = 0; i < len; i++) {
 140                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
 141                 int target;
 142
 143                 spin_lock(&irq->irq_lock);
 144
 145                 irq->targets = (val >> (i * 8)) & cpu_mask;
 146                 target = irq->targets ? __ffs(irq->targets) : 0;
 147                 irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
 148
 149                 spin_unlock(&irq->irq_lock);
 150                 vgic_put_irq(vcpu->kvm, irq);
 151         }
 152 }
 153
 154 static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
 155                                             gpa_t addr, unsigned int len)
 156 {
 157         u32 intid = addr & 0x0f;
 158         int i;
 159         u64 val = 0;
 160
 161         for (i = 0; i < len; i++) {
 162                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 163
 164                 val |= (u64)irq->source << (i * 8);
 165
 166                 vgic_put_irq(vcpu->kvm, irq);
 167         }
 168         return val;
 169 }
 170
 171 static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
 172                                      gpa_t addr, unsigned int len,
 173                                      unsigned long val)
 174 {
 175         u32 intid = addr & 0x0f;
 176         int i;
 177
 178         for (i = 0; i < len; i++) {
 179                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 180
 181                 spin_lock(&irq->irq_lock);
 182
 183                 irq->source &= ~((val >> (i * 8)) & 0xff);
 184                 if (!irq->source)
 185                         irq->pending_latch = false;
 186
 187                 spin_unlock(&irq->irq_lock);
 188                 vgic_put_irq(vcpu->kvm, irq);
 189         }
 190 }
 191
 192 static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
 193                                      gpa_t addr, unsigned int len,
 194                                      unsigned long val)
 195 {
 196         u32 intid = addr & 0x0f;
 197         int i;
 198
 199         for (i = 0; i < len; i++) {
 200                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 201
 202                 spin_lock(&irq->irq_lock);
 203
 204                 irq->source |= (val >> (i * 8)) & 0xff;
 205
 206                 if (irq->source) {
 207                         irq->pending_latch = true;
 208                         vgic_queue_irq_unlock(vcpu->kvm, irq);
 209                 } else {
 210                         spin_unlock(&irq->irq_lock);
 211                 }
 212                 vgic_put_irq(vcpu->kvm, irq);
 213         }
 214 }
 215
 216 #define GICC_ARCH_VERSION_V2    0x2
 217
 218 /* These are for userland accesses only, there is no guest-facing emulation. */
 219 static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
 220                                            gpa_t addr, unsigned int len)
 221 {
 222         struct vgic_vmcr vmcr;
 223         u32 val;
 224
 225         vgic_get_vmcr(vcpu, &vmcr);
 226
 227         switch (addr & 0xff) {
 228         case GIC_CPU_CTRL:
 229                 val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
 230                 val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;
 231                 val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;
 232                 val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;
 233                 val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
 234                 val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;
 235
 236                 break;
 237         case GIC_CPU_PRIMASK:
 238                 /*
 239                  * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
 240                  * the PMR field as GICH_VMCR.VMPriMask rather than
 241                  * GICC_PMR.Priority, so we expose the upper five bits of
 242                  * priority mask to userspace using the lower bits in the
 243                  * unsigned long.
 244                  */
 245                 val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>
 246                         GICV_PMR_PRIORITY_SHIFT;
 247                 break;
 248         case GIC_CPU_BINPOINT:
 249                 val = vmcr.bpr;
 250                 break;
 251         case GIC_CPU_ALIAS_BINPOINT:
 252                 val = vmcr.abpr;
 253                 break;
 254         case GIC_CPU_IDENT:
 255                 val = ((PRODUCT_ID_KVM << 20) |
 256                        (GICC_ARCH_VERSION_V2 << 16) |
 257                        IMPLEMENTER_ARM);
 258                 break;
 259         default:
 260                 return 0;
 261         }
 262
 263         return val;
 264 }
 265
 266 static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
 267                                    gpa_t addr, unsigned int len,
 268                                    unsigned long val)
 269 {
 270         struct vgic_vmcr vmcr;
 271
 272         vgic_get_vmcr(vcpu, &vmcr);
 273
 274         switch (addr & 0xff) {
 275         case GIC_CPU_CTRL:
 276                 vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);
 277                 vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);
 278                 vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);
 279                 vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);
 280                 vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);
 281                 vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);
 282
 283                 break;
 284         case GIC_CPU_PRIMASK:
 285                 /*
 286                  * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
 287                  * the PMR field as GICH_VMCR.VMPriMask rather than
 288                  * GICC_PMR.Priority, so we expose the upper five bits of
 289                  * priority mask to userspace using the lower bits in the
 290                  * unsigned long.
 291                  */
 292                 vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &
 293                         GICV_PMR_PRIORITY_MASK;
 294                 break;
 295         case GIC_CPU_BINPOINT:
 296                 vmcr.bpr = val;
 297                 break;
 298         case GIC_CPU_ALIAS_BINPOINT:
 299                 vmcr.abpr = val;
 300                 break;
 301         }
 302
 303         vgic_set_vmcr(vcpu, &vmcr);
 304 }
 305
 306 static const struct vgic_register_region vgic_v2_dist_registers[] = {
 307         REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
 308                 vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
 309                 VGIC_ACCESS_32bit),
 310         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
 311                 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
 312                 VGIC_ACCESS_32bit),
 313         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
 314                 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
 315                 VGIC_ACCESS_32bit),
 316         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
 317                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
 318                 VGIC_ACCESS_32bit),
 319         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
 320                 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
 321                 VGIC_ACCESS_32bit),
 322         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
 323                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
 324                 VGIC_ACCESS_32bit),
 325         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
 326                 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
 327                 VGIC_ACCESS_32bit),
 328         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
 329                 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
 330                 VGIC_ACCESS_32bit),
 331         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
 332                 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
 333                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 334         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
 335                 vgic_mmio_read_target, vgic_mmio_write_target, 8,
 336                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 337         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
 338                 vgic_mmio_read_config, vgic_mmio_write_config, 2,
 339                 VGIC_ACCESS_32bit),
 340         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
 341                 vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
 342                 VGIC_ACCESS_32bit),
 343         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
 344                 vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
 345                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 346         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
 347                 vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
 348                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 349 };
 350
 351 static const struct vgic_register_region vgic_v2_cpu_registers[] = {
 352         REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
 353                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 354                 VGIC_ACCESS_32bit),
 355         REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
 356                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 357                 VGIC_ACCESS_32bit),
 358         REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
 359                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 360                 VGIC_ACCESS_32bit),
 361         REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
 362                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 363                 VGIC_ACCESS_32bit),
 364         REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
 365                 vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
 366                 VGIC_ACCESS_32bit),
 367         REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
 368                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 369                 VGIC_ACCESS_32bit),
 370 };
 371
 372 unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
 373 {
 374         dev->regions = vgic_v2_dist_registers;
 375         dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
 376
 377         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 378
 379         return SZ_4K;
 380 }
 381
 382 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
 383 {
 384         const struct vgic_register_region *region;
 385         struct vgic_io_device iodev;
 386         struct vgic_reg_attr reg_attr;
 387         struct kvm_vcpu *vcpu;
 388         gpa_t addr;
 389         int ret;
 390
 391         ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
 392         if (ret)
 393                 return ret;
 394
 395         vcpu = reg_attr.vcpu;
 396         addr = reg_attr.addr;
 397
 398         switch (attr->group) {
 399         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
 400                 iodev.regions = vgic_v2_dist_registers;
 401                 iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
 402                 iodev.base_addr = 0;
 403                 break;
 404         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
 405                 iodev.regions = vgic_v2_cpu_registers;
 406                 iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
 407                 iodev.base_addr = 0;
 408                 break;
 409         default:
 410                 return -ENXIO;
 411         }
 412
 413         /* We only support aligned 32-bit accesses. */
 414         if (addr & 3)
 415                 return -ENXIO;
 416
 417         region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
 418         if (!region)
 419                 return -ENXIO;
 420
 421         return 0;
 422 }
 423
 424 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 425                           int offset, u32 *val)
 426 {
 427         struct vgic_io_device dev = {
 428                 .regions = vgic_v2_cpu_registers,
 429                 .nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
 430                 .iodev_type = IODEV_CPUIF,
 431         };
 432
 433         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 434 }
 435
 436 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 437                          int offset, u32 *val)
 438 {
 439         struct vgic_io_device dev = {
 440                 .regions = vgic_v2_dist_registers,
 441                 .nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
 442                 .iodev_type = IODEV_DIST,
 443         };
 444
 445         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 446 }