virt/kvm/arm/vgic/vgic-mmio-v2.c

   1 /*
   2  * VGICv2 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <kvm/iodev.h>
  18 #include <kvm/arm_vgic.h>
  19
  20 #include "vgic.h"
  21 #include "vgic-mmio.h"
  22
  23 static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
  24                                             gpa_t addr, unsigned int len)
  25 {
  26         u32 value;
  27
  28         switch (addr & 0x0c) {
  29         case GIC_DIST_CTRL:
  30                 value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
  31                 break;
  32         case GIC_DIST_CTR:
  33                 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
  34                 value = (value >> 5) - 1;
  35                 value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
  36                 break;
  37         case GIC_DIST_IIDR:
  38                 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
  39                 break;
  40         default:
  41                 return 0;
  42         }
  43
  44         return value;
  45 }
  46
  47 static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
  48                                     gpa_t addr, unsigned int len,
  49                                     unsigned long val)
  50 {
  51         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
  52         bool was_enabled = dist->enabled;
  53
  54         switch (addr & 0x0c) {
  55         case GIC_DIST_CTRL:
  56                 dist->enabled = val & GICD_ENABLE;
  57                 if (!was_enabled && dist->enabled)
  58                         vgic_kick_vcpus(vcpu->kvm);
  59                 break;
  60         case GIC_DIST_CTR:
  61         case GIC_DIST_IIDR:
  62                 /* Nothing to do */
  63                 return;
  64         }
  65 }
  66
  67 static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
  68                                  gpa_t addr, unsigned int len,
  69                                  unsigned long val)
  70 {
  71         int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
  72         int intid = val & 0xf;
  73         int targets = (val >> 16) & 0xff;
  74         int mode = (val >> 24) & 0x03;
  75         int c;
  76         struct kvm_vcpu *vcpu;
  77
  78         switch (mode) {
  79         case 0x0:               /* as specified by targets */
  80                 break;
  81         case 0x1:
  82                 targets = (1U << nr_vcpus) - 1;                 /* all, ... */
  83                 targets &= ~(1U << source_vcpu->vcpu_id);       /* but self */
  84                 break;
  85         case 0x2:               /* this very vCPU only */
  86                 targets = (1U << source_vcpu->vcpu_id);
  87                 break;
  88         case 0x3:               /* reserved */
  89                 return;
  90         }
  91
  92         kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
  93                 struct vgic_irq *irq;
  94
  95                 if (!(targets & (1U << c)))
  96                         continue;
  97
  98                 irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
  99
 100                 spin_lock(&irq->irq_lock);
 101                 irq->pending = true;
 102                 irq->source |= 1U << source_vcpu->vcpu_id;
 103
 104                 vgic_queue_irq_unlock(source_vcpu->kvm, irq);
 105                 vgic_put_irq(source_vcpu->kvm, irq);
 106         }
 107 }
 108
 109 static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
 110                                            gpa_t addr, unsigned int len)
 111 {
 112         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 113         int i;
 114         u64 val = 0;
 115
 116         for (i = 0; i < len; i++) {
 117                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 118
 119                 val |= (u64)irq->targets << (i * 8);
 120
 121                 vgic_put_irq(vcpu->kvm, irq);
 122         }
 123
 124         return val;
 125 }
 126
 127 static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
 128                                    gpa_t addr, unsigned int len,
 129                                    unsigned long val)
 130 {
 131         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 132         u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
 133         int i;
 134
 135         /* GICD_ITARGETSR[0-7] are read-only */
 136         if (intid < VGIC_NR_PRIVATE_IRQS)
 137                 return;
 138
 139         for (i = 0; i < len; i++) {
 140                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
 141                 int target;
 142
 143                 spin_lock(&irq->irq_lock);
 144
 145                 irq->targets = (val >> (i * 8)) & cpu_mask;
 146                 target = irq->targets ? __ffs(irq->targets) : 0;
 147                 irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
 148
 149                 spin_unlock(&irq->irq_lock);
 150                 vgic_put_irq(vcpu->kvm, irq);
 151         }
 152 }
 153
 154 static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
 155                                             gpa_t addr, unsigned int len)
 156 {
 157         u32 intid = addr & 0x0f;
 158         int i;
 159         u64 val = 0;
 160
 161         for (i = 0; i < len; i++) {
 162                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 163
 164                 val |= (u64)irq->source << (i * 8);
 165
 166                 vgic_put_irq(vcpu->kvm, irq);
 167         }
 168         return val;
 169 }
 170
 171 static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
 172                                      gpa_t addr, unsigned int len,
 173                                      unsigned long val)
 174 {
 175         u32 intid = addr & 0x0f;
 176         int i;
 177
 178         for (i = 0; i < len; i++) {
 179                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 180
 181                 spin_lock(&irq->irq_lock);
 182
 183                 irq->source &= ~((val >> (i * 8)) & 0xff);
 184                 if (!irq->source)
 185                         irq->pending = false;
 186
 187                 spin_unlock(&irq->irq_lock);
 188                 vgic_put_irq(vcpu->kvm, irq);
 189         }
 190 }
 191
 192 static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
 193                                      gpa_t addr, unsigned int len,
 194                                      unsigned long val)
 195 {
 196         u32 intid = addr & 0x0f;
 197         int i;
 198
 199         for (i = 0; i < len; i++) {
 200                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 201
 202                 spin_lock(&irq->irq_lock);
 203
 204                 irq->source |= (val >> (i * 8)) & 0xff;
 205
 206                 if (irq->source) {
 207                         irq->pending = true;
 208                         vgic_queue_irq_unlock(vcpu->kvm, irq);
 209                 } else {
 210                         spin_unlock(&irq->irq_lock);
 211                 }
 212                 vgic_put_irq(vcpu->kvm, irq);
 213         }
 214 }
 215
 216 static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 217 {
 218         if (kvm_vgic_global_state.type == VGIC_V2)
 219                 vgic_v2_set_vmcr(vcpu, vmcr);
 220         else
 221                 vgic_v3_set_vmcr(vcpu, vmcr);
 222 }
 223
 224 static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 225 {
 226         if (kvm_vgic_global_state.type == VGIC_V2)
 227                 vgic_v2_get_vmcr(vcpu, vmcr);
 228         else
 229                 vgic_v3_get_vmcr(vcpu, vmcr);
 230 }
 231
 232 #define GICC_ARCH_VERSION_V2    0x2
 233
 234 /* These are for userland accesses only, there is no guest-facing emulation. */
 235 static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
 236                                            gpa_t addr, unsigned int len)
 237 {
 238         struct vgic_vmcr vmcr;
 239         u32 val;
 240
 241         vgic_get_vmcr(vcpu, &vmcr);
 242
 243         switch (addr & 0xff) {
 244         case GIC_CPU_CTRL:
 245                 val = vmcr.ctlr;
 246                 break;
 247         case GIC_CPU_PRIMASK:
 248                 val = vmcr.pmr;
 249                 break;
 250         case GIC_CPU_BINPOINT:
 251                 val = vmcr.bpr;
 252                 break;
 253         case GIC_CPU_ALIAS_BINPOINT:
 254                 val = vmcr.abpr;
 255                 break;
 256         case GIC_CPU_IDENT:
 257                 val = ((PRODUCT_ID_KVM << 20) |
 258                        (GICC_ARCH_VERSION_V2 << 16) |
 259                        IMPLEMENTER_ARM);
 260                 break;
 261         default:
 262                 return 0;
 263         }
 264
 265         return val;
 266 }
 267
 268 static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
 269                                    gpa_t addr, unsigned int len,
 270                                    unsigned long val)
 271 {
 272         struct vgic_vmcr vmcr;
 273
 274         vgic_get_vmcr(vcpu, &vmcr);
 275
 276         switch (addr & 0xff) {
 277         case GIC_CPU_CTRL:
 278                 vmcr.ctlr = val;
 279                 break;
 280         case GIC_CPU_PRIMASK:
 281                 vmcr.pmr = val;
 282                 break;
 283         case GIC_CPU_BINPOINT:
 284                 vmcr.bpr = val;
 285                 break;
 286         case GIC_CPU_ALIAS_BINPOINT:
 287                 vmcr.abpr = val;
 288                 break;
 289         }
 290
 291         vgic_set_vmcr(vcpu, &vmcr);
 292 }
 293
 294 static const struct vgic_register_region vgic_v2_dist_registers[] = {
 295         REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
 296                 vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
 297                 VGIC_ACCESS_32bit),
 298         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
 299                 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
 300                 VGIC_ACCESS_32bit),
 301         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
 302                 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
 303                 VGIC_ACCESS_32bit),
 304         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
 305                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
 306                 VGIC_ACCESS_32bit),
 307         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
 308                 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
 309                 VGIC_ACCESS_32bit),
 310         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
 311                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
 312                 VGIC_ACCESS_32bit),
 313         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
 314                 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
 315                 VGIC_ACCESS_32bit),
 316         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
 317                 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
 318                 VGIC_ACCESS_32bit),
 319         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
 320                 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
 321                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 322         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
 323                 vgic_mmio_read_target, vgic_mmio_write_target, 8,
 324                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 325         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
 326                 vgic_mmio_read_config, vgic_mmio_write_config, 2,
 327                 VGIC_ACCESS_32bit),
 328         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
 329                 vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
 330                 VGIC_ACCESS_32bit),
 331         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
 332                 vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
 333                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 334         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
 335                 vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
 336                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 337 };
 338
 339 static const struct vgic_register_region vgic_v2_cpu_registers[] = {
 340         REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
 341                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 342                 VGIC_ACCESS_32bit),
 343         REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
 344                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 345                 VGIC_ACCESS_32bit),
 346         REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
 347                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 348                 VGIC_ACCESS_32bit),
 349         REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
 350                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 351                 VGIC_ACCESS_32bit),
 352         REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
 353                 vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
 354                 VGIC_ACCESS_32bit),
 355         REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
 356                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 357                 VGIC_ACCESS_32bit),
 358 };
 359
 360 unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
 361 {
 362         dev->regions = vgic_v2_dist_registers;
 363         dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
 364
 365         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 366
 367         return SZ_4K;
 368 }
 369
 370 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
 371 {
 372         int nr_irqs = dev->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 373         const struct vgic_register_region *regions;
 374         gpa_t addr;
 375         int nr_regions, i, len;
 376
 377         addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
 378
 379         switch (attr->group) {
 380         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
 381                 regions = vgic_v2_dist_registers;
 382                 nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
 383                 break;
 384         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
 385                 regions = vgic_v2_cpu_registers;
 386                 nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
 387                 break;
 388         default:
 389                 return -ENXIO;
 390         }
 391
 392         /* We only support aligned 32-bit accesses. */
 393         if (addr & 3)
 394                 return -ENXIO;
 395
 396         for (i = 0; i < nr_regions; i++) {
 397                 if (regions[i].bits_per_irq)
 398                         len = (regions[i].bits_per_irq * nr_irqs) / 8;
 399                 else
 400                         len = regions[i].len;
 401
 402                 if (regions[i].reg_offset <= addr &&
 403                     regions[i].reg_offset + len > addr)
 404                         return 0;
 405         }
 406
 407         return -ENXIO;
 408 }
 409
 410 /*
 411  * When userland tries to access the VGIC register handlers, we need to
 412  * create a usable struct vgic_io_device to be passed to the handlers and we
 413  * have to set up a buffer similar to what would have happened if a guest MMIO
 414  * access occurred, including doing endian conversions on BE systems.
 415  */
 416 static int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
 417                         bool is_write, int offset, u32 *val)
 418 {
 419         unsigned int len = 4;
 420         u8 buf[4];
 421         int ret;
 422
 423         if (is_write) {
 424                 vgic_data_host_to_mmio_bus(buf, len, *val);
 425                 ret = kvm_io_gic_ops.write(vcpu, &dev->dev, offset, len, buf);
 426         } else {
 427                 ret = kvm_io_gic_ops.read(vcpu, &dev->dev, offset, len, buf);
 428                 if (!ret)
 429                         *val = vgic_data_mmio_bus_to_host(buf, len);
 430         }
 431
 432         return ret;
 433 }
 434
 435 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 436                           int offset, u32 *val)
 437 {
 438         struct vgic_io_device dev = {
 439                 .regions = vgic_v2_cpu_registers,
 440                 .nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
 441                 .iodev_type = IODEV_CPUIF,
 442         };
 443
 444         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 445 }
 446
 447 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 448                          int offset, u32 *val)
 449 {
 450         struct vgic_io_device dev = {
 451                 .regions = vgic_v2_dist_registers,
 452                 .nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
 453                 .iodev_type = IODEV_DIST,
 454         };
 455
 456         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 457 }