2 * VGIC MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/bsearch.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/iodev.h>
19 #include <kvm/arm_vgic.h>
22 #include "vgic-mmio.h"
24 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
25 gpa_t addr, unsigned int len)
30 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
31 gpa_t addr, unsigned int len)
36 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
37 unsigned int len, unsigned long val)
43 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
44 * of the enabled bit, so there is only one function for both here.
46 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
47 gpa_t addr, unsigned int len)
49 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
53 /* Loop over all IRQs affected by this read */
54 for (i = 0; i < len * 8; i++) {
55 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
64 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
65 gpa_t addr, unsigned int len,
68 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
71 for_each_set_bit(i, &val, len * 8) {
72 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
74 spin_lock(&irq->irq_lock);
76 vgic_queue_irq_unlock(vcpu->kvm, irq);
80 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
81 gpa_t addr, unsigned int len,
84 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
87 for_each_set_bit(i, &val, len * 8) {
88 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
90 spin_lock(&irq->irq_lock);
94 spin_unlock(&irq->irq_lock);
98 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
99 gpa_t addr, unsigned int len)
101 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
105 /* Loop over all IRQs affected by this read */
106 for (i = 0; i < len * 8; i++) {
107 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
116 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
117 gpa_t addr, unsigned int len,
120 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
123 for_each_set_bit(i, &val, len * 8) {
124 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
126 spin_lock(&irq->irq_lock);
128 if (irq->config == VGIC_CONFIG_LEVEL)
129 irq->soft_pending = true;
131 vgic_queue_irq_unlock(vcpu->kvm, irq);
135 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
136 gpa_t addr, unsigned int len,
139 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
142 for_each_set_bit(i, &val, len * 8) {
143 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
145 spin_lock(&irq->irq_lock);
147 if (irq->config == VGIC_CONFIG_LEVEL) {
148 irq->soft_pending = false;
149 irq->pending = irq->line_level;
151 irq->pending = false;
154 spin_unlock(&irq->irq_lock);
158 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
159 gpa_t addr, unsigned int len)
161 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
165 /* Loop over all IRQs affected by this read */
166 for (i = 0; i < len * 8; i++) {
167 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
176 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
177 gpa_t addr, unsigned int len,
180 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
183 kvm_arm_halt_guest(vcpu->kvm);
184 for_each_set_bit(i, &val, len * 8) {
185 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
187 spin_lock(&irq->irq_lock);
189 * If this virtual IRQ was written into a list register, we
190 * have to make sure the CPU that runs the VCPU thread has
191 * synced back LR state to the struct vgic_irq. We can only
192 * know this for sure, when either this irq is not assigned to
193 * anyone's AP list anymore, or the VCPU thread is not
194 * running on any CPUs.
196 * In the opposite case, we know the VCPU thread may be on its
197 * way back from the guest and still has to sync back this
198 * IRQ, so we release and re-acquire the spin_lock to let the
199 * other thread sync back the IRQ.
201 while (irq->vcpu && /* IRQ may have state in an LR somewhere */
202 irq->vcpu->cpu != -1) /* VCPU thread is running */
203 cond_resched_lock(&irq->irq_lock);
206 spin_unlock(&irq->irq_lock);
208 kvm_arm_resume_guest(vcpu->kvm);
211 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
212 gpa_t addr, unsigned int len,
215 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
218 for_each_set_bit(i, &val, len * 8) {
219 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
221 spin_lock(&irq->irq_lock);
224 * If the IRQ was already active or there is no target VCPU
225 * assigned at the moment, then just proceed.
227 if (irq->active || !irq->target_vcpu) {
230 spin_unlock(&irq->irq_lock);
235 vgic_queue_irq_unlock(vcpu->kvm, irq);
239 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
240 gpa_t addr, unsigned int len)
242 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
246 for (i = 0; i < len; i++) {
247 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
249 val |= (u64)irq->priority << (i * 8);
256 * We currently don't handle changing the priority of an interrupt that
257 * is already pending on a VCPU. If there is a need for this, we would
258 * need to make this VCPU exit and re-evaluate the priorities, potentially
259 * leading to this interrupt getting presented now to the guest (if it has
260 * been masked by the priority mask before).
262 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
263 gpa_t addr, unsigned int len,
266 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
269 for (i = 0; i < len; i++) {
270 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
272 spin_lock(&irq->irq_lock);
273 /* Narrow the priority range to what we actually support */
274 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
275 spin_unlock(&irq->irq_lock);
279 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
280 gpa_t addr, unsigned int len)
282 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
286 for (i = 0; i < len * 4; i++) {
287 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
289 if (irq->config == VGIC_CONFIG_EDGE)
290 value |= (2U << (i * 2));
296 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
297 gpa_t addr, unsigned int len,
300 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
303 for (i = 0; i < len * 4; i++) {
304 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
307 * The configuration cannot be changed for SGIs in general,
308 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
309 * code relies on PPIs being level triggered, so we also
310 * make them read-only here.
312 if (intid + i < VGIC_NR_PRIVATE_IRQS)
315 spin_lock(&irq->irq_lock);
316 if (test_bit(i * 2 + 1, &val)) {
317 irq->config = VGIC_CONFIG_EDGE;
319 irq->config = VGIC_CONFIG_LEVEL;
320 irq->pending = irq->line_level | irq->soft_pending;
322 spin_unlock(&irq->irq_lock);
326 static int match_region(const void *key, const void *elt)
328 const unsigned int offset = (unsigned long)key;
329 const struct vgic_register_region *region = elt;
331 if (offset < region->reg_offset)
334 if (offset >= region->reg_offset + region->len)
340 /* Find the proper register handler entry given a certain address offset. */
341 static const struct vgic_register_region *
342 vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
345 return bsearch((void *)(uintptr_t)offset, region, nr_regions,
346 sizeof(region[0]), match_region);
350 * kvm_mmio_read_buf() returns a value in a format where it can be converted
351 * to a byte array and be directly observed as the guest wanted it to appear
352 * in memory if it had done the store itself, which is LE for the GIC, as the
353 * guest knows the GIC is always LE.
355 * We convert this value to the CPUs native format to deal with it as a data
358 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
360 unsigned long data = kvm_mmio_read_buf(val, len);
366 return le16_to_cpu(data);
368 return le32_to_cpu(data);
370 return le64_to_cpu(data);
375 * kvm_mmio_write_buf() expects a value in a format such that if converted to
376 * a byte array it is observed as the guest would see it if it could perform
377 * the load directly. Since the GIC is LE, and the guest knows this, the
378 * guest expects a value in little endian format.
380 * We convert the data value from the CPUs native format to LE so that the
381 * value is returned in the proper format.
383 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
390 data = cpu_to_le16(data);
393 data = cpu_to_le32(data);
396 data = cpu_to_le64(data);
399 kvm_mmio_write_buf(buf, len, data);
403 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
405 return container_of(dev, struct vgic_io_device, dev);
408 static bool check_region(const struct vgic_register_region *region,
411 if ((region->access_flags & VGIC_ACCESS_8bit) && len == 1)
413 if ((region->access_flags & VGIC_ACCESS_32bit) &&
414 len == sizeof(u32) && !(addr & 3))
416 if ((region->access_flags & VGIC_ACCESS_64bit) &&
417 len == sizeof(u64) && !(addr & 7))
423 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
424 gpa_t addr, int len, void *val)
426 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
427 const struct vgic_register_region *region;
428 struct kvm_vcpu *r_vcpu;
431 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
432 addr - iodev->base_addr);
433 if (!region || !check_region(region, addr, len)) {
438 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
439 data = region->read(r_vcpu, addr, len);
440 vgic_data_host_to_mmio_bus(val, len, data);
444 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
445 gpa_t addr, int len, const void *val)
447 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
448 const struct vgic_register_region *region;
449 struct kvm_vcpu *r_vcpu;
450 unsigned long data = vgic_data_mmio_bus_to_host(val, len);
452 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
453 addr - iodev->base_addr);
457 if (!check_region(region, addr, len))
460 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
461 region->write(r_vcpu, addr, len, data);
465 struct kvm_io_device_ops kvm_io_gic_ops = {
466 .read = dispatch_mmio_read,
467 .write = dispatch_mmio_write,
470 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
473 struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
479 len = vgic_v2_init_dist_iodev(io_device);
481 #ifdef CONFIG_KVM_ARM_VGIC_V3
483 len = vgic_v3_init_dist_iodev(io_device);
490 io_device->base_addr = dist_base_address;
491 io_device->redist_vcpu = NULL;
493 mutex_lock(&kvm->slots_lock);
494 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
495 len, &io_device->dev);
496 mutex_unlock(&kvm->slots_lock);