virt/kvm/arm/vgic/vgic-v2.c

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/irqchip/arm-gic.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_host.h>
  20 #include <kvm/arm_vgic.h>
  21 #include <asm/kvm_mmu.h>
  22
  23 #include "vgic.h"
  24
  25 static inline void vgic_v2_write_lr(int lr, u32 val)
  26 {
  27         void __iomem *base = kvm_vgic_global_state.vctrl_base;
  28
  29         writel_relaxed(val, base + GICH_LR0 + (lr * 4));
  30 }
  31
  32 void vgic_v2_init_lrs(void)
  33 {
  34         int i;
  35
  36         for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
  37                 vgic_v2_write_lr(i, 0);
  38 }
  39
  40 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
  41 {
  42         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  43
  44         cpuif->vgic_hcr |= GICH_HCR_UIE;
  45 }
  46
  47 static bool lr_signals_eoi_mi(u32 lr_val)
  48 {
  49         return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
  50                !(lr_val & GICH_LR_HW);
  51 }
  52
  53 /*
  54  * transfer the content of the LRs back into the corresponding ap_list:
  55  * - active bit is transferred as is
  56  * - pending bit is
  57  *   - transferred as is in case of edge sensitive IRQs
  58  *   - set to the line-level (resample time) for level sensitive IRQs
  59  */
  60 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
  61 {
  62         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  63         struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
  64         int lr;
  65
  66         cpuif->vgic_hcr &= ~GICH_HCR_UIE;
  67
  68         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  69                 u32 val = cpuif->vgic_lr[lr];
  70                 u32 intid = val & GICH_LR_VIRTUALID;
  71                 struct vgic_irq *irq;
  72
  73                 /* Notify fds when the guest EOI'ed a level-triggered SPI */
  74                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  75                         kvm_notify_acked_irq(vcpu->kvm, 0,
  76                                              intid - VGIC_NR_PRIVATE_IRQS);
  77
  78                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  79
  80                 spin_lock(&irq->irq_lock);
  81
  82                 /* Always preserve the active bit */
  83                 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
  84
  85                 /* Edge is the only case where we preserve the pending bit */
  86                 if (irq->config == VGIC_CONFIG_EDGE &&
  87                     (val & GICH_LR_PENDING_BIT)) {
  88                         irq->pending_latch = true;
  89
  90                         if (vgic_irq_is_sgi(intid)) {
  91                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  92
  93                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  94                                 irq->source |= (1 << cpuid);
  95                         }
  96                 }
  97
  98                 /*
  99                  * Clear soft pending state when level irqs have been acked.
 100                  * Always regenerate the pending state.
 101                  */
 102                 if (irq->config == VGIC_CONFIG_LEVEL) {
 103                         if (!(val & GICH_LR_PENDING_BIT))
 104                                 irq->pending_latch = false;
 105                 }
 106
 107                 spin_unlock(&irq->irq_lock);
 108                 vgic_put_irq(vcpu->kvm, irq);
 109         }
 110
 111         vgic_cpu->used_lrs = 0;
 112 }
 113
 114 /*
 115  * Populates the particular LR with the state of a given IRQ:
 116  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 117  * - for a level sensitive IRQ the pending state value is unchanged;
 118  *   it is dictated directly by the input level
 119  *
 120  * If @irq describes an SGI with multiple sources, we choose the
 121  * lowest-numbered source VCPU and clear that bit in the source bitmap.
 122  *
 123  * The irq_lock must be held by the caller.
 124  */
 125 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 126 {
 127         u32 val = irq->intid;
 128
 129         if (irq_is_pending(irq)) {
 130                 val |= GICH_LR_PENDING_BIT;
 131
 132                 if (irq->config == VGIC_CONFIG_EDGE)
 133                         irq->pending_latch = false;
 134
 135                 if (vgic_irq_is_sgi(irq->intid)) {
 136                         u32 src = ffs(irq->source);
 137
 138                         BUG_ON(!src);
 139                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 140                         irq->source &= ~(1 << (src - 1));
 141                         if (irq->source)
 142                                 irq->pending_latch = true;
 143                 }
 144         }
 145
 146         if (irq->active)
 147                 val |= GICH_LR_ACTIVE_BIT;
 148
 149         if (irq->hw) {
 150                 val |= GICH_LR_HW;
 151                 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
 152         } else {
 153                 if (irq->config == VGIC_CONFIG_LEVEL)
 154                         val |= GICH_LR_EOI;
 155         }
 156
 157         /* The GICv2 LR only holds five bits of priority. */
 158         val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 159
 160         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
 161 }
 162
 163 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
 164 {
 165         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
 166 }
 167
 168 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 169 {
 170         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 171         u32 vmcr;
 172
 173         vmcr  = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
 174         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
 175                 GICH_VMCR_ALIAS_BINPOINT_MASK;
 176         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
 177                 GICH_VMCR_BINPOINT_MASK;
 178         vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
 179                  GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 180
 181         cpu_if->vgic_vmcr = vmcr;
 182 }
 183
 184 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 185 {
 186         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 187         u32 vmcr;
 188
 189         vmcr = cpu_if->vgic_vmcr;
 190
 191         vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
 192                         GICH_VMCR_CTRL_SHIFT;
 193         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
 194                         GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 195         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
 196                         GICH_VMCR_BINPOINT_SHIFT;
 197         vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
 198                         GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
 199 }
 200
 201 void vgic_v2_enable(struct kvm_vcpu *vcpu)
 202 {
 203         /*
 204          * By forcing VMCR to zero, the GIC will restore the binary
 205          * points to their reset values. Anything else resets to zero
 206          * anyway.
 207          */
 208         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 209         vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
 210
 211         /* Get the show on the road... */
 212         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 213 }
 214
 215 /* check for overlapping regions and for regions crossing the end of memory */
 216 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
 217 {
 218         if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
 219                 return false;
 220         if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
 221                 return false;
 222
 223         if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
 224                 return true;
 225         if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
 226                 return true;
 227
 228         return false;
 229 }
 230
 231 int vgic_v2_map_resources(struct kvm *kvm)
 232 {
 233         struct vgic_dist *dist = &kvm->arch.vgic;
 234         int ret = 0;
 235
 236         if (vgic_ready(kvm))
 237                 goto out;
 238
 239         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 240             IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 241                 kvm_err("Need to set vgic cpu and dist addresses first\n");
 242                 ret = -ENXIO;
 243                 goto out;
 244         }
 245
 246         if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 247                 kvm_err("VGIC CPU and dist frames overlap\n");
 248                 ret = -EINVAL;
 249                 goto out;
 250         }
 251
 252         /*
 253          * Initialize the vgic if this hasn't already been done on demand by
 254          * accessing the vgic state from userspace.
 255          */
 256         ret = vgic_init(kvm);
 257         if (ret) {
 258                 kvm_err("Unable to initialize VGIC dynamic data structures\n");
 259                 goto out;
 260         }
 261
 262         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 263         if (ret) {
 264                 kvm_err("Unable to register VGIC MMIO regions\n");
 265                 goto out;
 266         }
 267
 268         if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 269                 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
 270                                             kvm_vgic_global_state.vcpu_base,
 271                                             KVM_VGIC_V2_CPU_SIZE, true);
 272                 if (ret) {
 273                         kvm_err("Unable to remap VGIC CPU to VCPU\n");
 274                         goto out;
 275                 }
 276         }
 277
 278         dist->ready = true;
 279
 280 out:
 281         return ret;
 282 }
 283
 284 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
 285
 286 /**
 287  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 288  * @node:       pointer to the DT node
 289  *
 290  * Returns 0 if a GICv2 has been found, returns an error code otherwise
 291  */
 292 int vgic_v2_probe(const struct gic_kvm_info *info)
 293 {
 294         int ret;
 295         u32 vtr;
 296
 297         if (!info->vctrl.start) {
 298                 kvm_err("GICH not present in the firmware table\n");
 299                 return -ENXIO;
 300         }
 301
 302         if (!PAGE_ALIGNED(info->vcpu.start) ||
 303             !PAGE_ALIGNED(resource_size(&info->vcpu))) {
 304                 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
 305                 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
 306                                                              resource_size(&info->vcpu));
 307                 if (!kvm_vgic_global_state.vcpu_base_va) {
 308                         kvm_err("Cannot ioremap GICV\n");
 309                         return -ENOMEM;
 310                 }
 311
 312                 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
 313                                              kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
 314                                              info->vcpu.start);
 315                 if (ret) {
 316                         kvm_err("Cannot map GICV into hyp\n");
 317                         goto out;
 318                 }
 319
 320                 static_branch_enable(&vgic_v2_cpuif_trap);
 321         }
 322
 323         kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
 324                                                    resource_size(&info->vctrl));
 325         if (!kvm_vgic_global_state.vctrl_base) {
 326                 kvm_err("Cannot ioremap GICH\n");
 327                 ret = -ENOMEM;
 328                 goto out;
 329         }
 330
 331         vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
 332         kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 333
 334         ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
 335                                      kvm_vgic_global_state.vctrl_base +
 336                                          resource_size(&info->vctrl),
 337                                      info->vctrl.start);
 338         if (ret) {
 339                 kvm_err("Cannot map VCTRL into hyp\n");
 340                 goto out;
 341         }
 342
 343         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 344         if (ret) {
 345                 kvm_err("Cannot register GICv2 KVM device\n");
 346                 goto out;
 347         }
 348
 349         kvm_vgic_global_state.can_emulate_gicv2 = true;
 350         kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 351         kvm_vgic_global_state.type = VGIC_V2;
 352         kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 353
 354         kvm_info("vgic-v2@%llx\n", info->vctrl.start);
 355
 356         return 0;
 357 out:
 358         if (kvm_vgic_global_state.vctrl_base)
 359                 iounmap(kvm_vgic_global_state.vctrl_base);
 360         if (kvm_vgic_global_state.vcpu_base_va)
 361                 iounmap(kvm_vgic_global_state.vcpu_base_va);
 362
 363         return ret;
 364 }
 365
 366 void vgic_v2_load(struct kvm_vcpu *vcpu)
 367 {
 368         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 369         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 370
 371         writel_relaxed(cpu_if->vgic_vmcr, vgic->vctrl_base + GICH_VMCR);
 372 }
 373
 374 void vgic_v2_put(struct kvm_vcpu *vcpu)
 375 {
 376         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 377         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 378
 379         cpu_if->vgic_vmcr = readl_relaxed(vgic->vctrl_base + GICH_VMCR);
 380 }