virt/kvm/arm/vgic/vgic-v2.c

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/irqchip/arm-gic.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_host.h>
  20 #include <kvm/arm_vgic.h>
  21 #include <asm/kvm_mmu.h>
  22
  23 #include "vgic.h"
  24
  25 static inline void vgic_v2_write_lr(int lr, u32 val)
  26 {
  27         void __iomem *base = kvm_vgic_global_state.vctrl_base;
  28
  29         writel_relaxed(val, base + GICH_LR0 + (lr * 4));
  30 }
  31
  32 void vgic_v2_init_lrs(void)
  33 {
  34         int i;
  35
  36         for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
  37                 vgic_v2_write_lr(i, 0);
  38 }
  39
  40 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
  41 {
  42         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  43
  44         cpuif->vgic_hcr |= GICH_HCR_UIE;
  45 }
  46
  47 static bool lr_signals_eoi_mi(u32 lr_val)
  48 {
  49         return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
  50                !(lr_val & GICH_LR_HW);
  51 }
  52
  53 /*
  54  * transfer the content of the LRs back into the corresponding ap_list:
  55  * - active bit is transferred as is
  56  * - pending bit is
  57  *   - transferred as is in case of edge sensitive IRQs
  58  *   - set to the line-level (resample time) for level sensitive IRQs
  59  */
  60 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
  61 {
  62         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  63         struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
  64         int lr;
  65
  66         cpuif->vgic_hcr &= ~GICH_HCR_UIE;
  67
  68         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  69                 u32 val = cpuif->vgic_lr[lr];
  70                 u32 intid = val & GICH_LR_VIRTUALID;
  71                 struct vgic_irq *irq;
  72
  73                 /* Notify fds when the guest EOI'ed a level-triggered SPI */
  74                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  75                         kvm_notify_acked_irq(vcpu->kvm, 0,
  76                                              intid - VGIC_NR_PRIVATE_IRQS);
  77
  78                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  79
  80                 spin_lock(&irq->irq_lock);
  81
  82                 /* Always preserve the active bit */
  83                 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
  84
  85                 /* Edge is the only case where we preserve the pending bit */
  86                 if (irq->config == VGIC_CONFIG_EDGE &&
  87                     (val & GICH_LR_PENDING_BIT)) {
  88                         irq->pending_latch = true;
  89
  90                         if (vgic_irq_is_sgi(intid)) {
  91                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  92
  93                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  94                                 irq->source |= (1 << cpuid);
  95                         }
  96                 }
  97
  98                 /*
  99                  * Clear soft pending state when level irqs have been acked.
 100                  * Always regenerate the pending state.
 101                  */
 102                 if (irq->config == VGIC_CONFIG_LEVEL) {
 103                         if (!(val & GICH_LR_PENDING_BIT))
 104                                 irq->pending_latch = false;
 105                 }
 106
 107                 spin_unlock(&irq->irq_lock);
 108                 vgic_put_irq(vcpu->kvm, irq);
 109         }
 110
 111         vgic_cpu->used_lrs = 0;
 112 }
 113
 114 /*
 115  * Populates the particular LR with the state of a given IRQ:
 116  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 117  * - for a level sensitive IRQ the pending state value is unchanged;
 118  *   it is dictated directly by the input level
 119  *
 120  * If @irq describes an SGI with multiple sources, we choose the
 121  * lowest-numbered source VCPU and clear that bit in the source bitmap.
 122  *
 123  * The irq_lock must be held by the caller.
 124  */
 125 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 126 {
 127         u32 val = irq->intid;
 128
 129         if (irq_is_pending(irq)) {
 130                 val |= GICH_LR_PENDING_BIT;
 131
 132                 if (irq->config == VGIC_CONFIG_EDGE)
 133                         irq->pending_latch = false;
 134
 135                 if (vgic_irq_is_sgi(irq->intid)) {
 136                         u32 src = ffs(irq->source);
 137
 138                         BUG_ON(!src);
 139                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 140                         irq->source &= ~(1 << (src - 1));
 141                         if (irq->source)
 142                                 irq->pending_latch = true;
 143                 }
 144         }
 145
 146         if (irq->active)
 147                 val |= GICH_LR_ACTIVE_BIT;
 148
 149         if (irq->hw) {
 150                 val |= GICH_LR_HW;
 151                 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
 152                 /*
 153                  * Never set pending+active on a HW interrupt, as the
 154                  * pending state is kept at the physical distributor
 155                  * level.
 156                  */
 157                 if (irq->active && irq_is_pending(irq))
 158                         val &= ~GICH_LR_PENDING_BIT;
 159         } else {
 160                 if (irq->config == VGIC_CONFIG_LEVEL)
 161                         val |= GICH_LR_EOI;
 162         }
 163
 164         /* The GICv2 LR only holds five bits of priority. */
 165         val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 166
 167         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
 168 }
 169
 170 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
 171 {
 172         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
 173 }
 174
 175 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 176 {
 177         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 178         u32 vmcr;
 179
 180         vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
 181                 GICH_VMCR_ENABLE_GRP0_MASK;
 182         vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
 183                 GICH_VMCR_ENABLE_GRP1_MASK;
 184         vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
 185                 GICH_VMCR_ACK_CTL_MASK;
 186         vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
 187                 GICH_VMCR_FIQ_EN_MASK;
 188         vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
 189                 GICH_VMCR_CBPR_MASK;
 190         vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
 191                 GICH_VMCR_EOI_MODE_MASK;
 192         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
 193                 GICH_VMCR_ALIAS_BINPOINT_MASK;
 194         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
 195                 GICH_VMCR_BINPOINT_MASK;
 196         vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
 197                  GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 198
 199         cpu_if->vgic_vmcr = vmcr;
 200 }
 201
 202 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 203 {
 204         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 205         u32 vmcr;
 206
 207         vmcr = cpu_if->vgic_vmcr;
 208
 209         vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
 210                 GICH_VMCR_ENABLE_GRP0_SHIFT;
 211         vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
 212                 GICH_VMCR_ENABLE_GRP1_SHIFT;
 213         vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
 214                 GICH_VMCR_ACK_CTL_SHIFT;
 215         vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
 216                 GICH_VMCR_FIQ_EN_SHIFT;
 217         vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
 218                 GICH_VMCR_CBPR_SHIFT;
 219         vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
 220                 GICH_VMCR_EOI_MODE_SHIFT;
 221
 222         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
 223                         GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 224         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
 225                         GICH_VMCR_BINPOINT_SHIFT;
 226         vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
 227                         GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
 228 }
 229
 230 void vgic_v2_enable(struct kvm_vcpu *vcpu)
 231 {
 232         /*
 233          * By forcing VMCR to zero, the GIC will restore the binary
 234          * points to their reset values. Anything else resets to zero
 235          * anyway.
 236          */
 237         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 238         vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
 239
 240         /* Get the show on the road... */
 241         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 242 }
 243
 244 /* check for overlapping regions and for regions crossing the end of memory */
 245 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
 246 {
 247         if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
 248                 return false;
 249         if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
 250                 return false;
 251
 252         if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
 253                 return true;
 254         if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
 255                 return true;
 256
 257         return false;
 258 }
 259
 260 int vgic_v2_map_resources(struct kvm *kvm)
 261 {
 262         struct vgic_dist *dist = &kvm->arch.vgic;
 263         int ret = 0;
 264
 265         if (vgic_ready(kvm))
 266                 goto out;
 267
 268         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 269             IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 270                 kvm_err("Need to set vgic cpu and dist addresses first\n");
 271                 ret = -ENXIO;
 272                 goto out;
 273         }
 274
 275         if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 276                 kvm_err("VGIC CPU and dist frames overlap\n");
 277                 ret = -EINVAL;
 278                 goto out;
 279         }
 280
 281         /*
 282          * Initialize the vgic if this hasn't already been done on demand by
 283          * accessing the vgic state from userspace.
 284          */
 285         ret = vgic_init(kvm);
 286         if (ret) {
 287                 kvm_err("Unable to initialize VGIC dynamic data structures\n");
 288                 goto out;
 289         }
 290
 291         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 292         if (ret) {
 293                 kvm_err("Unable to register VGIC MMIO regions\n");
 294                 goto out;
 295         }
 296
 297         if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 298                 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
 299                                             kvm_vgic_global_state.vcpu_base,
 300                                             KVM_VGIC_V2_CPU_SIZE, true);
 301                 if (ret) {
 302                         kvm_err("Unable to remap VGIC CPU to VCPU\n");
 303                         goto out;
 304                 }
 305         }
 306
 307         dist->ready = true;
 308
 309 out:
 310         return ret;
 311 }
 312
 313 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
 314
 315 /**
 316  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 317  * @node:       pointer to the DT node
 318  *
 319  * Returns 0 if a GICv2 has been found, returns an error code otherwise
 320  */
 321 int vgic_v2_probe(const struct gic_kvm_info *info)
 322 {
 323         int ret;
 324         u32 vtr;
 325
 326         if (!info->vctrl.start) {
 327                 kvm_err("GICH not present in the firmware table\n");
 328                 return -ENXIO;
 329         }
 330
 331         if (!PAGE_ALIGNED(info->vcpu.start) ||
 332             !PAGE_ALIGNED(resource_size(&info->vcpu))) {
 333                 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
 334                 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
 335                                                              resource_size(&info->vcpu));
 336                 if (!kvm_vgic_global_state.vcpu_base_va) {
 337                         kvm_err("Cannot ioremap GICV\n");
 338                         return -ENOMEM;
 339                 }
 340
 341                 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
 342                                              kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
 343                                              info->vcpu.start);
 344                 if (ret) {
 345                         kvm_err("Cannot map GICV into hyp\n");
 346                         goto out;
 347                 }
 348
 349                 static_branch_enable(&vgic_v2_cpuif_trap);
 350         }
 351
 352         kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
 353                                                    resource_size(&info->vctrl));
 354         if (!kvm_vgic_global_state.vctrl_base) {
 355                 kvm_err("Cannot ioremap GICH\n");
 356                 ret = -ENOMEM;
 357                 goto out;
 358         }
 359
 360         vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
 361         kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 362
 363         ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
 364                                      kvm_vgic_global_state.vctrl_base +
 365                                          resource_size(&info->vctrl),
 366                                      info->vctrl.start);
 367         if (ret) {
 368                 kvm_err("Cannot map VCTRL into hyp\n");
 369                 goto out;
 370         }
 371
 372         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 373         if (ret) {
 374                 kvm_err("Cannot register GICv2 KVM device\n");
 375                 goto out;
 376         }
 377
 378         kvm_vgic_global_state.can_emulate_gicv2 = true;
 379         kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 380         kvm_vgic_global_state.type = VGIC_V2;
 381         kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 382
 383         kvm_info("vgic-v2@%llx\n", info->vctrl.start);
 384
 385         return 0;
 386 out:
 387         if (kvm_vgic_global_state.vctrl_base)
 388                 iounmap(kvm_vgic_global_state.vctrl_base);
 389         if (kvm_vgic_global_state.vcpu_base_va)
 390                 iounmap(kvm_vgic_global_state.vcpu_base_va);
 391
 392         return ret;
 393 }
 394
 395 void vgic_v2_load(struct kvm_vcpu *vcpu)
 396 {
 397         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 398         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 399
 400         writel_relaxed(cpu_if->vgic_vmcr, vgic->vctrl_base + GICH_VMCR);
 401 }
 402
 403 void vgic_v2_put(struct kvm_vcpu *vcpu)
 404 {
 405         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 406         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 407
 408         cpu_if->vgic_vmcr = readl_relaxed(vgic->vctrl_base + GICH_VMCR);
 409 }