2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/irqchip/arm-gic.h>
18 #include <linux/kvm.h>
19 #include <linux/kvm_host.h>
24 * Call this function to convert a u64 value to an unsigned long * bitmask
25 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
27 * Warning: Calling this function may modify *val.
29 static unsigned long *u64_to_bitmask(u64 *val)
31 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
32 *val = (*val >> 32) | (*val << 32);
34 return (unsigned long *)val;
37 void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
39 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
41 if (cpuif->vgic_misr & GICH_MISR_EOI) {
42 u64 eisr = cpuif->vgic_eisr;
43 unsigned long *eisr_bmap = u64_to_bitmask(&eisr);
46 for_each_set_bit(lr, eisr_bmap, kvm_vgic_global_state.nr_lr) {
47 u32 intid = cpuif->vgic_lr[lr] & GICH_LR_VIRTUALID;
49 WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);
51 kvm_notify_acked_irq(vcpu->kvm, 0,
52 intid - VGIC_NR_PRIVATE_IRQS);
56 /* check and disable underflow maintenance IRQ */
57 cpuif->vgic_hcr &= ~GICH_HCR_UIE;
60 * In the next iterations of the vcpu loop, if we sync the
61 * vgic state after flushing it, but before entering the guest
62 * (this happens for pending signals and vmid rollovers), then
63 * make sure we don't pick up any old maintenance interrupts
69 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
71 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
73 cpuif->vgic_hcr |= GICH_HCR_UIE;
77 * transfer the content of the LRs back into the corresponding ap_list:
78 * - active bit is transferred as is
80 * - transferred as is in case of edge sensitive IRQs
81 * - set to the line-level (resample time) for level sensitive IRQs
83 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
85 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
88 for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
89 u32 val = cpuif->vgic_lr[lr];
90 u32 intid = val & GICH_LR_VIRTUALID;
93 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
95 spin_lock(&irq->irq_lock);
97 /* Always preserve the active bit */
98 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
100 /* Edge is the only case where we preserve the pending bit */
101 if (irq->config == VGIC_CONFIG_EDGE &&
102 (val & GICH_LR_PENDING_BIT)) {
105 if (vgic_irq_is_sgi(intid)) {
106 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
108 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
109 irq->source |= (1 << cpuid);
113 /* Clear soft pending state when level IRQs have been acked */
114 if (irq->config == VGIC_CONFIG_LEVEL &&
115 !(val & GICH_LR_PENDING_BIT)) {
116 irq->soft_pending = false;
117 irq->pending = irq->line_level;
120 spin_unlock(&irq->irq_lock);
125 * Populates the particular LR with the state of a given IRQ:
126 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
127 * - for a level sensitive IRQ the pending state value is unchanged;
128 * it is dictated directly by the input level
130 * If @irq describes an SGI with multiple sources, we choose the
131 * lowest-numbered source VCPU and clear that bit in the source bitmap.
133 * The irq_lock must be held by the caller.
135 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
137 u32 val = irq->intid;
140 val |= GICH_LR_PENDING_BIT;
142 if (irq->config == VGIC_CONFIG_EDGE)
143 irq->pending = false;
145 if (vgic_irq_is_sgi(irq->intid)) {
146 u32 src = ffs(irq->source);
149 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
150 irq->source &= ~(1 << (src - 1));
157 val |= GICH_LR_ACTIVE_BIT;
161 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
163 if (irq->config == VGIC_CONFIG_LEVEL)
167 /* The GICv2 LR only holds five bits of priority. */
168 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
170 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
173 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
175 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;