virt/kvm/arm/vgic/vgic-v3.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  13  */
  14
  15 #include <linux/irqchip/arm-gic-v3.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/arm_vgic.h>
  19 #include <asm/kvm_mmu.h>
  20 #include <asm/kvm_asm.h>
  21
  22 #include "vgic.h"
  23
  24 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
  25 {
  26         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  27
  28         cpuif->vgic_hcr |= ICH_HCR_UIE;
  29 }
  30
  31 static bool lr_signals_eoi_mi(u64 lr_val)
  32 {
  33         return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
  34                !(lr_val & ICH_LR_HW);
  35 }
  36
  37 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
  38 {
  39         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  40         struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
  41         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  42         int lr;
  43
  44         cpuif->vgic_hcr &= ~ICH_HCR_UIE;
  45
  46         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  47                 u64 val = cpuif->vgic_lr[lr];
  48                 u32 intid;
  49                 struct vgic_irq *irq;
  50
  51                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  52                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
  53                 else
  54                         intid = val & GICH_LR_VIRTUALID;
  55
  56                 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
  57                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  58                         kvm_notify_acked_irq(vcpu->kvm, 0,
  59                                              intid - VGIC_NR_PRIVATE_IRQS);
  60
  61                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  62                 if (!irq)       /* An LPI could have been unmapped. */
  63                         continue;
  64
  65                 spin_lock(&irq->irq_lock);
  66
  67                 /* Always preserve the active bit */
  68                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
  69
  70                 /* Edge is the only case where we preserve the pending bit */
  71                 if (irq->config == VGIC_CONFIG_EDGE &&
  72                     (val & ICH_LR_PENDING_BIT)) {
  73                         irq->pending_latch = true;
  74
  75                         if (vgic_irq_is_sgi(intid) &&
  76                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
  77                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  78
  79                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  80                                 irq->source |= (1 << cpuid);
  81                         }
  82                 }
  83
  84                 /*
  85                  * Clear soft pending state when level irqs have been acked.
  86                  * Always regenerate the pending state.
  87                  */
  88                 if (irq->config == VGIC_CONFIG_LEVEL) {
  89                         if (!(val & ICH_LR_PENDING_BIT))
  90                                 irq->pending_latch = false;
  91                 }
  92
  93                 spin_unlock(&irq->irq_lock);
  94                 vgic_put_irq(vcpu->kvm, irq);
  95         }
  96
  97         vgic_cpu->used_lrs = 0;
  98 }
  99
 100 /* Requires the irq to be locked already */
 101 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 102 {
 103         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 104         u64 val = irq->intid;
 105
 106         if (irq_is_pending(irq)) {
 107                 val |= ICH_LR_PENDING_BIT;
 108
 109                 if (irq->config == VGIC_CONFIG_EDGE)
 110                         irq->pending_latch = false;
 111
 112                 if (vgic_irq_is_sgi(irq->intid) &&
 113                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 114                         u32 src = ffs(irq->source);
 115
 116                         BUG_ON(!src);
 117                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 118                         irq->source &= ~(1 << (src - 1));
 119                         if (irq->source)
 120                                 irq->pending_latch = true;
 121                 }
 122         }
 123
 124         if (irq->active)
 125                 val |= ICH_LR_ACTIVE_BIT;
 126
 127         if (irq->hw) {
 128                 val |= ICH_LR_HW;
 129                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
 130         } else {
 131                 if (irq->config == VGIC_CONFIG_LEVEL)
 132                         val |= ICH_LR_EOI;
 133         }
 134
 135         /*
 136          * We currently only support Group1 interrupts, which is a
 137          * known defect. This needs to be addressed at some point.
 138          */
 139         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 140                 val |= ICH_LR_GROUP;
 141
 142         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 143
 144         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
 145 }
 146
 147 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
 148 {
 149         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
 150 }
 151
 152 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 153 {
 154         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 155         u32 vmcr;
 156
 157         /*
 158          * Ignore the FIQen bit, because GIC emulation always implies
 159          * SRE=1 which means the vFIQEn bit is also RES1.
 160          */
 161         vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
 162                  ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
 163         vmcr |= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
 164         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 165         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 166         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 167         vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
 168         vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 169
 170         cpu_if->vgic_vmcr = vmcr;
 171 }
 172
 173 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 174 {
 175         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 176         u32 vmcr;
 177
 178         vmcr = cpu_if->vgic_vmcr;
 179
 180         /*
 181          * Ignore the FIQen bit, because GIC emulation always implies
 182          * SRE=1 which means the vFIQEn bit is also RES1.
 183          */
 184         vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
 185                         ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
 186         vmcrp->ctlr |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 187         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 188         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 189         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 190         vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
 191         vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
 192 }
 193
 194 #define INITIAL_PENDBASER_VALUE                                           \
 195         (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)            | \
 196         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)      | \
 197         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
 198
 199 void vgic_v3_enable(struct kvm_vcpu *vcpu)
 200 {
 201         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 202
 203         /*
 204          * By forcing VMCR to zero, the GIC will restore the binary
 205          * points to their reset values. Anything else resets to zero
 206          * anyway.
 207          */
 208         vgic_v3->vgic_vmcr = 0;
 209         vgic_v3->vgic_elrsr = ~0;
 210
 211         /*
 212          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 213          * way, so we force SRE to 1 to demonstrate this to the guest.
 214          * Also, we don't support any form of IRQ/FIQ bypass.
 215          * This goes with the spec allowing the value to be RAO/WI.
 216          */
 217         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
 218                 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
 219                                      ICC_SRE_EL1_DFB |
 220                                      ICC_SRE_EL1_SRE);
 221                 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
 222         } else {
 223                 vgic_v3->vgic_sre = 0;
 224         }
 225
 226         vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
 227                                            ICH_VTR_ID_BITS_MASK) >>
 228                                            ICH_VTR_ID_BITS_SHIFT;
 229         vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
 230                                             ICH_VTR_PRI_BITS_MASK) >>
 231                                             ICH_VTR_PRI_BITS_SHIFT) + 1;
 232
 233         /* Get the show on the road... */
 234         vgic_v3->vgic_hcr = ICH_HCR_EN;
 235 }
 236
 237 /* check for overlapping regions and for regions crossing the end of memory */
 238 static bool vgic_v3_check_base(struct kvm *kvm)
 239 {
 240         struct vgic_dist *d = &kvm->arch.vgic;
 241         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
 242
 243         redist_size *= atomic_read(&kvm->online_vcpus);
 244
 245         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
 246                 return false;
 247         if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
 248                 return false;
 249
 250         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
 251                 return true;
 252         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
 253                 return true;
 254
 255         return false;
 256 }
 257
 258 int vgic_v3_map_resources(struct kvm *kvm)
 259 {
 260         int ret = 0;
 261         struct vgic_dist *dist = &kvm->arch.vgic;
 262
 263         if (vgic_ready(kvm))
 264                 goto out;
 265
 266         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 267             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
 268                 kvm_err("Need to set vgic distributor addresses first\n");
 269                 ret = -ENXIO;
 270                 goto out;
 271         }
 272
 273         if (!vgic_v3_check_base(kvm)) {
 274                 kvm_err("VGIC redist and dist frames overlap\n");
 275                 ret = -EINVAL;
 276                 goto out;
 277         }
 278
 279         /*
 280          * For a VGICv3 we require the userland to explicitly initialize
 281          * the VGIC before we need to use it.
 282          */
 283         if (!vgic_initialized(kvm)) {
 284                 ret = -EBUSY;
 285                 goto out;
 286         }
 287
 288         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 289         if (ret) {
 290                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
 291                 goto out;
 292         }
 293
 294         ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
 295         if (ret) {
 296                 kvm_err("Unable to register VGICv3 redist MMIO regions\n");
 297                 goto out;
 298         }
 299
 300         if (vgic_has_its(kvm)) {
 301                 ret = vgic_register_its_iodevs(kvm);
 302                 if (ret) {
 303                         kvm_err("Unable to register VGIC ITS MMIO regions\n");
 304                         goto out;
 305                 }
 306         }
 307
 308         dist->ready = true;
 309
 310 out:
 311         return ret;
 312 }
 313
 314 /**
 315  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 316  * @node:       pointer to the DT node
 317  *
 318  * Returns 0 if a GICv3 has been found, returns an error code otherwise
 319  */
 320 int vgic_v3_probe(const struct gic_kvm_info *info)
 321 {
 322         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 323         int ret;
 324
 325         /*
 326          * The ListRegs field is 5 bits, but there is a architectural
 327          * maximum of 16 list registers. Just ignore bit 4...
 328          */
 329         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 330         kvm_vgic_global_state.can_emulate_gicv2 = false;
 331         kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 332
 333         if (!info->vcpu.start) {
 334                 kvm_info("GICv3: no GICV resource entry\n");
 335                 kvm_vgic_global_state.vcpu_base = 0;
 336         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
 337                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 338                         (unsigned long long)info->vcpu.start);
 339                 kvm_vgic_global_state.vcpu_base = 0;
 340         } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
 341                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 342                         (unsigned long long)resource_size(&info->vcpu),
 343                         PAGE_SIZE);
 344                 kvm_vgic_global_state.vcpu_base = 0;
 345         } else {
 346                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 347                 kvm_vgic_global_state.can_emulate_gicv2 = true;
 348                 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 349                 if (ret) {
 350                         kvm_err("Cannot register GICv2 KVM device.\n");
 351                         return ret;
 352                 }
 353                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
 354         }
 355         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
 356         if (ret) {
 357                 kvm_err("Cannot register GICv3 KVM device.\n");
 358                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
 359                 return ret;
 360         }
 361
 362         if (kvm_vgic_global_state.vcpu_base == 0)
 363                 kvm_info("disabling GICv2 emulation\n");
 364
 365         kvm_vgic_global_state.vctrl_base = NULL;
 366         kvm_vgic_global_state.type = VGIC_V3;
 367         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 368
 369         return 0;
 370 }
 371
 372 void vgic_v3_load(struct kvm_vcpu *vcpu)
 373 {
 374         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 375
 376         /*
 377          * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
 378          * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
 379          * VMCR_EL2 save/restore in the world switch.
 380          */
 381         if (likely(cpu_if->vgic_sre))
 382                 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
 383 }
 384
 385 void vgic_v3_put(struct kvm_vcpu *vcpu)
 386 {
 387         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 388
 389         if (likely(cpu_if->vgic_sre))
 390                 cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);
 391 }