2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 #include <linux/irqchip/arm-gic-v3.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/arm_vgic.h>
19 #include <asm/kvm_mmu.h>
20 #include <asm/kvm_asm.h>
24 void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
26 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
27 u32 model = vcpu->kvm->arch.vgic.vgic_model;
29 if (cpuif->vgic_misr & ICH_MISR_EOI) {
30 unsigned long eisr_bmap = cpuif->vgic_eisr;
33 for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
35 u64 val = cpuif->vgic_lr[lr];
37 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
38 intid = val & ICH_LR_VIRTUAL_ID_MASK;
40 intid = val & GICH_LR_VIRTUALID;
42 WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
44 /* Only SPIs require notification */
45 if (vgic_valid_spi(vcpu->kvm, intid))
46 kvm_notify_acked_irq(vcpu->kvm, 0,
47 intid - VGIC_NR_PRIVATE_IRQS);
51 * In the next iterations of the vcpu loop, if we sync
52 * the vgic state after flushing it, but before
53 * entering the guest (this happens for pending
54 * signals and vmid rollovers), then make sure we
55 * don't pick up any old maintenance interrupts here.
60 cpuif->vgic_hcr &= ~ICH_HCR_UIE;
63 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
65 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
67 cpuif->vgic_hcr |= ICH_HCR_UIE;
70 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
72 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
73 u32 model = vcpu->kvm->arch.vgic.vgic_model;
76 for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
77 u64 val = cpuif->vgic_lr[lr];
81 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
82 intid = val & ICH_LR_VIRTUAL_ID_MASK;
84 intid = val & GICH_LR_VIRTUALID;
85 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
86 if (!irq) /* An LPI could have been unmapped. */
89 spin_lock(&irq->irq_lock);
91 /* Always preserve the active bit */
92 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
94 /* Edge is the only case where we preserve the pending bit */
95 if (irq->config == VGIC_CONFIG_EDGE &&
96 (val & ICH_LR_PENDING_BIT)) {
99 if (vgic_irq_is_sgi(intid) &&
100 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
101 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
103 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
104 irq->source |= (1 << cpuid);
109 * Clear soft pending state when level irqs have been acked.
110 * Always regenerate the pending state.
112 if (irq->config == VGIC_CONFIG_LEVEL) {
113 if (!(val & ICH_LR_PENDING_BIT))
114 irq->soft_pending = false;
116 irq->pending = irq->line_level || irq->soft_pending;
119 spin_unlock(&irq->irq_lock);
120 vgic_put_irq(vcpu->kvm, irq);
124 /* Requires the irq to be locked already */
125 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
127 u32 model = vcpu->kvm->arch.vgic.vgic_model;
128 u64 val = irq->intid;
131 val |= ICH_LR_PENDING_BIT;
133 if (irq->config == VGIC_CONFIG_EDGE)
134 irq->pending = false;
136 if (vgic_irq_is_sgi(irq->intid) &&
137 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
138 u32 src = ffs(irq->source);
141 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
142 irq->source &= ~(1 << (src - 1));
149 val |= ICH_LR_ACTIVE_BIT;
153 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
155 if (irq->config == VGIC_CONFIG_LEVEL)
160 * We currently only support Group1 interrupts, which is a
161 * known defect. This needs to be addressed at some point.
163 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
166 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
168 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
171 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
173 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
176 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
180 vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
181 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
182 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
183 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
185 vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
188 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
190 u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
192 vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
193 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
194 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
195 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
198 #define INITIAL_PENDBASER_VALUE \
199 (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \
200 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \
201 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
203 void vgic_v3_enable(struct kvm_vcpu *vcpu)
205 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
208 * By forcing VMCR to zero, the GIC will restore the binary
209 * points to their reset values. Anything else resets to zero
212 vgic_v3->vgic_vmcr = 0;
213 vgic_v3->vgic_elrsr = ~0;
216 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
217 * way, so we force SRE to 1 to demonstrate this to the guest.
218 * This goes with the spec allowing the value to be RAO/WI.
220 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
221 vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
222 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
224 vgic_v3->vgic_sre = 0;
227 /* Get the show on the road... */
228 vgic_v3->vgic_hcr = ICH_HCR_EN;
231 /* check for overlapping regions and for regions crossing the end of memory */
232 static bool vgic_v3_check_base(struct kvm *kvm)
234 struct vgic_dist *d = &kvm->arch.vgic;
235 gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
237 redist_size *= atomic_read(&kvm->online_vcpus);
239 if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
241 if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
244 if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
246 if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
252 int vgic_v3_map_resources(struct kvm *kvm)
255 struct vgic_dist *dist = &kvm->arch.vgic;
260 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
261 IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
262 kvm_err("Need to set vgic distributor addresses first\n");
267 if (!vgic_v3_check_base(kvm)) {
268 kvm_err("VGIC redist and dist frames overlap\n");
274 * For a VGICv3 we require the userland to explicitly initialize
275 * the VGIC before we need to use it.
277 if (!vgic_initialized(kvm)) {
282 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
284 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
288 ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
290 kvm_err("Unable to register VGICv3 redist MMIO regions\n");
294 if (vgic_has_its(kvm)) {
295 ret = vgic_register_its_iodevs(kvm);
297 kvm_err("Unable to register VGIC ITS MMIO regions\n");
309 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
310 * @node: pointer to the DT node
312 * Returns 0 if a GICv3 has been found, returns an error code otherwise
314 int vgic_v3_probe(const struct gic_kvm_info *info)
316 u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
320 * The ListRegs field is 5 bits, but there is a architectural
321 * maximum of 16 list registers. Just ignore bit 4...
323 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
324 kvm_vgic_global_state.can_emulate_gicv2 = false;
326 if (!info->vcpu.start) {
327 kvm_info("GICv3: no GICV resource entry\n");
328 kvm_vgic_global_state.vcpu_base = 0;
329 } else if (!PAGE_ALIGNED(info->vcpu.start)) {
330 pr_warn("GICV physical address 0x%llx not page aligned\n",
331 (unsigned long long)info->vcpu.start);
332 kvm_vgic_global_state.vcpu_base = 0;
333 } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
334 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
335 (unsigned long long)resource_size(&info->vcpu),
337 kvm_vgic_global_state.vcpu_base = 0;
339 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
340 kvm_vgic_global_state.can_emulate_gicv2 = true;
341 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
343 kvm_err("Cannot register GICv2 KVM device.\n");
346 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
348 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
350 kvm_err("Cannot register GICv3 KVM device.\n");
351 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
355 if (kvm_vgic_global_state.vcpu_base == 0)
356 kvm_info("disabling GICv2 emulation\n");
358 kvm_vgic_global_state.vctrl_base = NULL;
359 kvm_vgic_global_state.type = VGIC_V3;
360 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;