2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 #include <linux/irqchip/arm-gic-v3.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/arm_vgic.h>
19 #include <asm/kvm_mmu.h>
20 #include <asm/kvm_asm.h>
24 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
26 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
28 cpuif->vgic_hcr |= ICH_HCR_UIE;
31 static bool lr_signals_eoi_mi(u64 lr_val)
33 return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
34 !(lr_val & ICH_LR_HW);
37 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
39 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
40 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
41 u32 model = vcpu->kvm->arch.vgic.vgic_model;
44 cpuif->vgic_hcr &= ~ICH_HCR_UIE;
46 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
47 u64 val = cpuif->vgic_lr[lr];
51 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
52 intid = val & ICH_LR_VIRTUAL_ID_MASK;
54 intid = val & GICH_LR_VIRTUALID;
56 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
57 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
58 kvm_notify_acked_irq(vcpu->kvm, 0,
59 intid - VGIC_NR_PRIVATE_IRQS);
61 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
62 if (!irq) /* An LPI could have been unmapped. */
65 spin_lock(&irq->irq_lock);
67 /* Always preserve the active bit */
68 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
70 /* Edge is the only case where we preserve the pending bit */
71 if (irq->config == VGIC_CONFIG_EDGE &&
72 (val & ICH_LR_PENDING_BIT)) {
73 irq->pending_latch = true;
75 if (vgic_irq_is_sgi(intid) &&
76 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
77 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
79 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
80 irq->source |= (1 << cpuid);
85 * Clear soft pending state when level irqs have been acked.
86 * Always regenerate the pending state.
88 if (irq->config == VGIC_CONFIG_LEVEL) {
89 if (!(val & ICH_LR_PENDING_BIT))
90 irq->pending_latch = false;
93 spin_unlock(&irq->irq_lock);
94 vgic_put_irq(vcpu->kvm, irq);
97 vgic_cpu->used_lrs = 0;
100 /* Requires the irq to be locked already */
101 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
103 u32 model = vcpu->kvm->arch.vgic.vgic_model;
104 u64 val = irq->intid;
106 if (irq_is_pending(irq)) {
107 val |= ICH_LR_PENDING_BIT;
109 if (irq->config == VGIC_CONFIG_EDGE)
110 irq->pending_latch = false;
112 if (vgic_irq_is_sgi(irq->intid) &&
113 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
114 u32 src = ffs(irq->source);
117 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
118 irq->source &= ~(1 << (src - 1));
120 irq->pending_latch = true;
125 val |= ICH_LR_ACTIVE_BIT;
129 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
131 if (irq->config == VGIC_CONFIG_LEVEL)
136 * We currently only support Group1 interrupts, which is a
137 * known defect. This needs to be addressed at some point.
139 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
142 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
144 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
147 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
149 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
152 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
154 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
158 * Ignore the FIQen bit, because GIC emulation always implies
159 * SRE=1 which means the vFIQEn bit is also RES1.
161 vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
162 ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
163 vmcr |= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
164 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
165 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
166 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
167 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
168 vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
170 cpu_if->vgic_vmcr = vmcr;
173 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
175 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
178 vmcr = cpu_if->vgic_vmcr;
181 * Ignore the FIQen bit, because GIC emulation always implies
182 * SRE=1 which means the vFIQEn bit is also RES1.
184 vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
185 ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
186 vmcrp->ctlr |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
187 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
188 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
189 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
190 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
191 vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
194 #define INITIAL_PENDBASER_VALUE \
195 (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \
196 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \
197 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
199 void vgic_v3_enable(struct kvm_vcpu *vcpu)
201 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
204 * By forcing VMCR to zero, the GIC will restore the binary
205 * points to their reset values. Anything else resets to zero
208 vgic_v3->vgic_vmcr = 0;
209 vgic_v3->vgic_elrsr = ~0;
212 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
213 * way, so we force SRE to 1 to demonstrate this to the guest.
214 * Also, we don't support any form of IRQ/FIQ bypass.
215 * This goes with the spec allowing the value to be RAO/WI.
217 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
218 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
221 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
223 vgic_v3->vgic_sre = 0;
226 vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
227 ICH_VTR_ID_BITS_MASK) >>
228 ICH_VTR_ID_BITS_SHIFT;
229 vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
230 ICH_VTR_PRI_BITS_MASK) >>
231 ICH_VTR_PRI_BITS_SHIFT) + 1;
233 /* Get the show on the road... */
234 vgic_v3->vgic_hcr = ICH_HCR_EN;
237 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
239 struct kvm_vcpu *vcpu;
240 int byte_offset, bit_nr;
247 vcpu = irq->target_vcpu;
251 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
253 byte_offset = irq->intid / BITS_PER_BYTE;
254 bit_nr = irq->intid % BITS_PER_BYTE;
255 ptr = pendbase + byte_offset;
257 ret = kvm_read_guest(kvm, ptr, &val, 1);
261 status = val & (1 << bit_nr);
263 spin_lock(&irq->irq_lock);
264 if (irq->target_vcpu != vcpu) {
265 spin_unlock(&irq->irq_lock);
268 irq->pending_latch = status;
269 vgic_queue_irq_unlock(vcpu->kvm, irq);
272 /* clear consumed data */
273 val &= ~(1 << bit_nr);
274 ret = kvm_write_guest(kvm, ptr, &val, 1);
282 * vgic_its_save_pending_tables - Save the pending tables into guest RAM
283 * kvm lock and all vcpu lock must be held
285 int vgic_v3_save_pending_tables(struct kvm *kvm)
287 struct vgic_dist *dist = &kvm->arch.vgic;
288 int last_byte_offset = -1;
289 struct vgic_irq *irq;
292 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
293 int byte_offset, bit_nr;
294 struct kvm_vcpu *vcpu;
299 vcpu = irq->target_vcpu;
303 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
305 byte_offset = irq->intid / BITS_PER_BYTE;
306 bit_nr = irq->intid % BITS_PER_BYTE;
307 ptr = pendbase + byte_offset;
309 if (byte_offset != last_byte_offset) {
310 ret = kvm_read_guest(kvm, ptr, &val, 1);
313 last_byte_offset = byte_offset;
316 stored = val & (1U << bit_nr);
317 if (stored == irq->pending_latch)
320 if (irq->pending_latch)
323 val &= ~(1 << bit_nr);
325 ret = kvm_write_guest(kvm, ptr, &val, 1);
332 /* check for overlapping regions and for regions crossing the end of memory */
333 static bool vgic_v3_check_base(struct kvm *kvm)
335 struct vgic_dist *d = &kvm->arch.vgic;
336 gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
338 redist_size *= atomic_read(&kvm->online_vcpus);
340 if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
342 if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
345 if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
347 if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
353 int vgic_v3_map_resources(struct kvm *kvm)
356 struct vgic_dist *dist = &kvm->arch.vgic;
361 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
362 IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
363 kvm_err("Need to set vgic distributor addresses first\n");
368 if (!vgic_v3_check_base(kvm)) {
369 kvm_err("VGIC redist and dist frames overlap\n");
375 * For a VGICv3 we require the userland to explicitly initialize
376 * the VGIC before we need to use it.
378 if (!vgic_initialized(kvm)) {
383 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
385 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
389 ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
391 kvm_err("Unable to register VGICv3 redist MMIO regions\n");
395 if (vgic_has_its(kvm)) {
396 ret = vgic_register_its_iodevs(kvm);
398 kvm_err("Unable to register VGIC ITS MMIO regions\n");
410 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
411 * @node: pointer to the DT node
413 * Returns 0 if a GICv3 has been found, returns an error code otherwise
415 int vgic_v3_probe(const struct gic_kvm_info *info)
417 u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
421 * The ListRegs field is 5 bits, but there is a architectural
422 * maximum of 16 list registers. Just ignore bit 4...
424 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
425 kvm_vgic_global_state.can_emulate_gicv2 = false;
426 kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
428 if (!info->vcpu.start) {
429 kvm_info("GICv3: no GICV resource entry\n");
430 kvm_vgic_global_state.vcpu_base = 0;
431 } else if (!PAGE_ALIGNED(info->vcpu.start)) {
432 pr_warn("GICV physical address 0x%llx not page aligned\n",
433 (unsigned long long)info->vcpu.start);
434 kvm_vgic_global_state.vcpu_base = 0;
435 } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
436 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
437 (unsigned long long)resource_size(&info->vcpu),
439 kvm_vgic_global_state.vcpu_base = 0;
441 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
442 kvm_vgic_global_state.can_emulate_gicv2 = true;
443 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
445 kvm_err("Cannot register GICv2 KVM device.\n");
448 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
450 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
452 kvm_err("Cannot register GICv3 KVM device.\n");
453 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
457 if (kvm_vgic_global_state.vcpu_base == 0)
458 kvm_info("disabling GICv2 emulation\n");
460 kvm_vgic_global_state.vctrl_base = NULL;
461 kvm_vgic_global_state.type = VGIC_V3;
462 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
467 void vgic_v3_load(struct kvm_vcpu *vcpu)
469 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
472 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
473 * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
474 * VMCR_EL2 save/restore in the world switch.
476 if (likely(cpu_if->vgic_sre))
477 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
480 void vgic_v3_put(struct kvm_vcpu *vcpu)
482 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
484 if (likely(cpu_if->vgic_sre))
485 cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);