2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 #include <linux/irqchip/arm-gic-v3.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/arm_vgic.h>
19 #include <asm/kvm_mmu.h>
20 #include <asm/kvm_asm.h>
24 void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
26 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
27 u32 model = vcpu->kvm->arch.vgic.vgic_model;
29 if (cpuif->vgic_misr & ICH_MISR_EOI) {
30 unsigned long eisr_bmap = cpuif->vgic_eisr;
33 for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
35 u64 val = cpuif->vgic_lr[lr];
37 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
38 intid = val & ICH_LR_VIRTUAL_ID_MASK;
40 intid = val & GICH_LR_VIRTUALID;
42 WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
44 kvm_notify_acked_irq(vcpu->kvm, 0,
45 intid - VGIC_NR_PRIVATE_IRQS);
49 * In the next iterations of the vcpu loop, if we sync
50 * the vgic state after flushing it, but before
51 * entering the guest (this happens for pending
52 * signals and vmid rollovers), then make sure we
53 * don't pick up any old maintenance interrupts here.
58 cpuif->vgic_hcr &= ~ICH_HCR_UIE;
61 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
63 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
65 cpuif->vgic_hcr |= ICH_HCR_UIE;
68 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
70 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
71 u32 model = vcpu->kvm->arch.vgic.vgic_model;
74 for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
75 u64 val = cpuif->vgic_lr[lr];
79 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
80 intid = val & ICH_LR_VIRTUAL_ID_MASK;
82 intid = val & GICH_LR_VIRTUALID;
83 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
85 spin_lock(&irq->irq_lock);
87 /* Always preserve the active bit */
88 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
90 /* Edge is the only case where we preserve the pending bit */
91 if (irq->config == VGIC_CONFIG_EDGE &&
92 (val & ICH_LR_PENDING_BIT)) {
95 if (vgic_irq_is_sgi(intid) &&
96 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
97 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
99 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
100 irq->source |= (1 << cpuid);
104 /* Clear soft pending state when level irqs have been acked */
105 if (irq->config == VGIC_CONFIG_LEVEL &&
106 !(val & ICH_LR_PENDING_BIT)) {
107 irq->soft_pending = false;
108 irq->pending = irq->line_level;
111 spin_unlock(&irq->irq_lock);
115 /* Requires the irq to be locked already */
116 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
118 u32 model = vcpu->kvm->arch.vgic.vgic_model;
119 u64 val = irq->intid;
122 val |= ICH_LR_PENDING_BIT;
124 if (irq->config == VGIC_CONFIG_EDGE)
125 irq->pending = false;
127 if (vgic_irq_is_sgi(irq->intid) &&
128 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
129 u32 src = ffs(irq->source);
132 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
133 irq->source &= ~(1 << (src - 1));
140 val |= ICH_LR_ACTIVE_BIT;
144 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
146 if (irq->config == VGIC_CONFIG_LEVEL)
151 * We currently only support Group1 interrupts, which is a
152 * known defect. This needs to be addressed at some point.
154 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
157 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
159 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
162 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
164 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
167 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
171 vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
172 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
173 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
174 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
176 vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
179 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
181 u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
183 vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
184 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
185 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
186 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
190 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
191 * @node: pointer to the DT node
193 * Returns 0 if a GICv3 has been found, returns an error code otherwise
195 int vgic_v3_probe(const struct gic_kvm_info *info)
197 u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
200 * The ListRegs field is 5 bits, but there is a architectural
201 * maximum of 16 list registers. Just ignore bit 4...
203 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
204 kvm_vgic_global_state.can_emulate_gicv2 = false;
206 if (!info->vcpu.start) {
207 kvm_info("GICv3: no GICV resource entry\n");
208 kvm_vgic_global_state.vcpu_base = 0;
209 } else if (!PAGE_ALIGNED(info->vcpu.start)) {
210 pr_warn("GICV physical address 0x%llx not page aligned\n",
211 (unsigned long long)info->vcpu.start);
212 kvm_vgic_global_state.vcpu_base = 0;
213 } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
214 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
215 (unsigned long long)resource_size(&info->vcpu),
217 kvm_vgic_global_state.vcpu_base = 0;
219 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
220 kvm_vgic_global_state.can_emulate_gicv2 = true;
221 kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
222 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
224 if (kvm_vgic_global_state.vcpu_base == 0)
225 kvm_info("disabling GICv2 emulation\n");
226 kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
228 kvm_vgic_global_state.vctrl_base = NULL;
229 kvm_vgic_global_state.type = VGIC_V3;
230 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;