2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 #include <linux/irqchip/arm-gic-v3.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/arm_vgic.h>
19 #include <asm/kvm_mmu.h>
20 #include <asm/kvm_asm.h>
24 void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
26 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
27 u32 model = vcpu->kvm->arch.vgic.vgic_model;
29 if (cpuif->vgic_misr & ICH_MISR_EOI) {
30 unsigned long eisr_bmap = cpuif->vgic_eisr;
33 for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
35 u64 val = cpuif->vgic_lr[lr];
37 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
38 intid = val & ICH_LR_VIRTUAL_ID_MASK;
40 intid = val & GICH_LR_VIRTUALID;
42 WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
44 /* Only SPIs require notification */
45 if (vgic_valid_spi(vcpu->kvm, intid))
46 kvm_notify_acked_irq(vcpu->kvm, 0,
47 intid - VGIC_NR_PRIVATE_IRQS);
51 * In the next iterations of the vcpu loop, if we sync
52 * the vgic state after flushing it, but before
53 * entering the guest (this happens for pending
54 * signals and vmid rollovers), then make sure we
55 * don't pick up any old maintenance interrupts here.
60 cpuif->vgic_hcr &= ~ICH_HCR_UIE;
63 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
65 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
67 cpuif->vgic_hcr |= ICH_HCR_UIE;
70 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
72 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
73 u32 model = vcpu->kvm->arch.vgic.vgic_model;
76 for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
77 u64 val = cpuif->vgic_lr[lr];
81 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
82 intid = val & ICH_LR_VIRTUAL_ID_MASK;
84 intid = val & GICH_LR_VIRTUALID;
85 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
86 if (!irq) /* An LPI could have been unmapped. */
89 spin_lock(&irq->irq_lock);
91 /* Always preserve the active bit */
92 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
94 /* Edge is the only case where we preserve the pending bit */
95 if (irq->config == VGIC_CONFIG_EDGE &&
96 (val & ICH_LR_PENDING_BIT)) {
97 irq->pending_latch = true;
99 if (vgic_irq_is_sgi(intid) &&
100 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
101 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
103 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
104 irq->source |= (1 << cpuid);
109 * Clear soft pending state when level irqs have been acked.
110 * Always regenerate the pending state.
112 if (irq->config == VGIC_CONFIG_LEVEL) {
113 if (!(val & ICH_LR_PENDING_BIT))
114 irq->pending_latch = false;
117 spin_unlock(&irq->irq_lock);
118 vgic_put_irq(vcpu->kvm, irq);
122 /* Requires the irq to be locked already */
123 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
125 u32 model = vcpu->kvm->arch.vgic.vgic_model;
126 u64 val = irq->intid;
128 if (irq_is_pending(irq)) {
129 val |= ICH_LR_PENDING_BIT;
131 if (irq->config == VGIC_CONFIG_EDGE)
132 irq->pending_latch = false;
134 if (vgic_irq_is_sgi(irq->intid) &&
135 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
136 u32 src = ffs(irq->source);
139 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
140 irq->source &= ~(1 << (src - 1));
142 irq->pending_latch = true;
147 val |= ICH_LR_ACTIVE_BIT;
151 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
153 if (irq->config == VGIC_CONFIG_LEVEL)
158 * We currently only support Group1 interrupts, which is a
159 * known defect. This needs to be addressed at some point.
161 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
164 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
166 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
169 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
171 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
174 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
179 * Ignore the FIQen bit, because GIC emulation always implies
180 * SRE=1 which means the vFIQEn bit is also RES1.
182 vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
183 ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
184 vmcr |= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
185 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
186 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
187 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
188 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
189 vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
191 vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
194 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
196 u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
199 * Ignore the FIQen bit, because GIC emulation always implies
200 * SRE=1 which means the vFIQEn bit is also RES1.
202 vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
203 ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
204 vmcrp->ctlr |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
205 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
206 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
207 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
208 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
209 vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
212 #define INITIAL_PENDBASER_VALUE \
213 (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \
214 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \
215 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
217 void vgic_v3_enable(struct kvm_vcpu *vcpu)
219 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
222 * By forcing VMCR to zero, the GIC will restore the binary
223 * points to their reset values. Anything else resets to zero
226 vgic_v3->vgic_vmcr = 0;
227 vgic_v3->vgic_elrsr = ~0;
230 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
231 * way, so we force SRE to 1 to demonstrate this to the guest.
232 * Also, we don't support any form of IRQ/FIQ bypass.
233 * This goes with the spec allowing the value to be RAO/WI.
235 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
236 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
239 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
241 vgic_v3->vgic_sre = 0;
244 vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
245 ICH_VTR_ID_BITS_MASK) >>
246 ICH_VTR_ID_BITS_SHIFT;
247 vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
248 ICH_VTR_PRI_BITS_MASK) >>
249 ICH_VTR_PRI_BITS_SHIFT) + 1;
251 /* Get the show on the road... */
252 vgic_v3->vgic_hcr = ICH_HCR_EN;
255 /* check for overlapping regions and for regions crossing the end of memory */
256 static bool vgic_v3_check_base(struct kvm *kvm)
258 struct vgic_dist *d = &kvm->arch.vgic;
259 gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
261 redist_size *= atomic_read(&kvm->online_vcpus);
263 if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
265 if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
268 if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
270 if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
276 int vgic_v3_map_resources(struct kvm *kvm)
279 struct vgic_dist *dist = &kvm->arch.vgic;
284 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
285 IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
286 kvm_err("Need to set vgic distributor addresses first\n");
291 if (!vgic_v3_check_base(kvm)) {
292 kvm_err("VGIC redist and dist frames overlap\n");
298 * For a VGICv3 we require the userland to explicitly initialize
299 * the VGIC before we need to use it.
301 if (!vgic_initialized(kvm)) {
306 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
308 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
312 ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
314 kvm_err("Unable to register VGICv3 redist MMIO regions\n");
318 if (vgic_has_its(kvm)) {
319 ret = vgic_register_its_iodevs(kvm);
321 kvm_err("Unable to register VGIC ITS MMIO regions\n");
333 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
334 * @node: pointer to the DT node
336 * Returns 0 if a GICv3 has been found, returns an error code otherwise
338 int vgic_v3_probe(const struct gic_kvm_info *info)
340 u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
344 * The ListRegs field is 5 bits, but there is a architectural
345 * maximum of 16 list registers. Just ignore bit 4...
347 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
348 kvm_vgic_global_state.can_emulate_gicv2 = false;
349 kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
351 if (!info->vcpu.start) {
352 kvm_info("GICv3: no GICV resource entry\n");
353 kvm_vgic_global_state.vcpu_base = 0;
354 } else if (!PAGE_ALIGNED(info->vcpu.start)) {
355 pr_warn("GICV physical address 0x%llx not page aligned\n",
356 (unsigned long long)info->vcpu.start);
357 kvm_vgic_global_state.vcpu_base = 0;
358 } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
359 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
360 (unsigned long long)resource_size(&info->vcpu),
362 kvm_vgic_global_state.vcpu_base = 0;
364 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
365 kvm_vgic_global_state.can_emulate_gicv2 = true;
366 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
368 kvm_err("Cannot register GICv2 KVM device.\n");
371 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
373 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
375 kvm_err("Cannot register GICv3 KVM device.\n");
376 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
380 if (kvm_vgic_global_state.vcpu_base == 0)
381 kvm_info("disabling GICv2 emulation\n");
383 kvm_vgic_global_state.vctrl_base = NULL;
384 kvm_vgic_global_state.type = VGIC_V3;
385 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;