2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __KVM_ARM_VGIC_NEW_H__
17 #define __KVM_ARM_VGIC_NEW_H__
19 #include <linux/irqchip/arm-gic-common.h>
21 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */
22 #define IMPLEMENTER_ARM 0x43b
24 #define VGIC_ADDR_UNDEF (-1)
25 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
27 #define INTERRUPT_ID_BITS_SPIS 10
28 #define INTERRUPT_ID_BITS_ITS 16
29 #define VGIC_PRI_BITS 5
31 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
33 #define VGIC_AFFINITY_0_SHIFT 0
34 #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
35 #define VGIC_AFFINITY_1_SHIFT 8
36 #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
37 #define VGIC_AFFINITY_2_SHIFT 16
38 #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
39 #define VGIC_AFFINITY_3_SHIFT 24
40 #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
42 #define VGIC_AFFINITY_LEVEL(reg, level) \
43 ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
44 >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
47 * The Userspace encodes the affinity differently from the MPIDR,
48 * Below macro converts vgic userspace format to MPIDR reg format.
50 #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
51 VGIC_AFFINITY_LEVEL(val, 1) | \
52 VGIC_AFFINITY_LEVEL(val, 2) | \
53 VGIC_AFFINITY_LEVEL(val, 3))
56 * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
57 * below macros are defined for CPUREG encoding.
59 #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
60 #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
61 #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
62 #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
63 #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
64 #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
65 #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
66 #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
67 #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
68 #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
70 #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
71 KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
72 KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
73 KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
74 KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
76 static inline bool irq_is_pending(struct vgic_irq *irq)
78 if (irq->config == VGIC_CONFIG_EDGE)
79 return irq->pending_latch;
81 return irq->pending_latch || irq->line_level;
85 * This struct provides an intermediate representation of the fields contained
86 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
87 * state to userspace can generate either GICv2 or GICv3 CPU interface
88 * registers regardless of the hardware backed GIC used.
94 u32 pmr; /* Priority mask field in the GICC_PMR and
95 * ICC_PMR_EL1 priority field format */
96 /* Below member variable are valid only for GICv3 */
101 struct vgic_reg_attr {
102 struct kvm_vcpu *vcpu;
106 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
107 struct vgic_reg_attr *reg_attr);
108 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
109 struct vgic_reg_attr *reg_attr);
110 const struct vgic_register_region *
111 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
112 gpa_t addr, int len);
113 struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
115 void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
116 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
117 void vgic_kick_vcpus(struct kvm *kvm);
119 int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
120 phys_addr_t addr, phys_addr_t alignment);
122 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
123 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
124 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
125 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
126 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
127 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
128 int offset, u32 *val);
129 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
130 int offset, u32 *val);
131 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
132 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
133 void vgic_v2_enable(struct kvm_vcpu *vcpu);
134 int vgic_v2_probe(const struct gic_kvm_info *info);
135 int vgic_v2_map_resources(struct kvm *kvm);
136 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
139 void vgic_v2_init_lrs(void);
140 void vgic_v2_load(struct kvm_vcpu *vcpu);
141 void vgic_v2_put(struct kvm_vcpu *vcpu);
143 static inline void vgic_get_irq_kref(struct vgic_irq *irq)
145 if (irq->intid < VGIC_MIN_LPI)
148 kref_get(&irq->refcount);
151 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
152 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
153 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
154 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
155 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
156 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
157 void vgic_v3_enable(struct kvm_vcpu *vcpu);
158 int vgic_v3_probe(const struct gic_kvm_info *info);
159 int vgic_v3_map_resources(struct kvm *kvm);
160 int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t dist_base_address);
162 void vgic_v3_load(struct kvm_vcpu *vcpu);
163 void vgic_v3_put(struct kvm_vcpu *vcpu);
165 int vgic_register_its_iodevs(struct kvm *kvm);
166 bool vgic_has_its(struct kvm *kvm);
167 int kvm_vgic_register_its_device(void);
168 void vgic_enable_lpis(struct kvm_vcpu *vcpu);
169 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
170 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
171 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
172 int offset, u32 *val);
173 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
174 int offset, u32 *val);
175 int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
177 int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
179 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
180 u32 intid, u64 *val);
181 int kvm_register_vgic_device(unsigned long type);
182 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
183 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
184 int vgic_lazy_init(struct kvm *kvm);
185 int vgic_init(struct kvm *kvm);
187 int vgic_debug_init(struct kvm *kvm);
188 int vgic_debug_destroy(struct kvm *kvm);