2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
34 #include <linux/pm_runtime.h>
37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
53 #define INTEL_RC6_ENABLE (1<<0)
54 #define INTEL_RC6p_ENABLE (1<<1)
55 #define INTEL_RC6pp_ENABLE (1<<2)
57 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
58 * framebuffer contents in-memory, aiming at reducing the required bandwidth
59 * during in-memory transfers and, therefore, reduce the power packet.
61 * The benefits of FBC are mostly visible with solid backgrounds and
62 * variation-less patterns.
64 * FBC-related functionality can be enabled by the means of the
65 * i915.i915_enable_fbc parameter
68 static void i8xx_disable_fbc(struct drm_device *dev)
70 struct drm_i915_private *dev_priv = dev->dev_private;
73 /* Disable compression */
74 fbc_ctl = I915_READ(FBC_CONTROL);
75 if ((fbc_ctl & FBC_CTL_EN) == 0)
78 fbc_ctl &= ~FBC_CTL_EN;
79 I915_WRITE(FBC_CONTROL, fbc_ctl);
81 /* Wait for compressing bit to clear */
82 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
83 DRM_DEBUG_KMS("FBC idle timed out\n");
87 DRM_DEBUG_KMS("disabled FBC\n");
90 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
92 struct drm_device *dev = crtc->dev;
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 struct drm_framebuffer *fb = crtc->fb;
95 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
96 struct drm_i915_gem_object *obj = intel_fb->obj;
97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
100 u32 fbc_ctl, fbc_ctl2;
102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
106 /* FBC_CTL wants 64B units */
107 cfb_pitch = (cfb_pitch / 64) - 1;
108 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
111 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
112 I915_WRITE(FBC_TAG + (i * 4), 0);
115 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
117 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
118 I915_WRITE(FBC_FENCE_OFF, crtc->y);
121 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
123 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
124 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
125 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
126 fbc_ctl |= obj->fence_reg;
127 I915_WRITE(FBC_CONTROL, fbc_ctl);
129 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
130 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
133 static bool i8xx_fbc_enabled(struct drm_device *dev)
135 struct drm_i915_private *dev_priv = dev->dev_private;
137 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
140 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
142 struct drm_device *dev = crtc->dev;
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 struct drm_framebuffer *fb = crtc->fb;
145 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
146 struct drm_i915_gem_object *obj = intel_fb->obj;
147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
148 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
149 unsigned long stall_watermark = 200;
152 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
153 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
154 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
156 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
157 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
158 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
159 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
162 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
164 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
167 static void g4x_disable_fbc(struct drm_device *dev)
169 struct drm_i915_private *dev_priv = dev->dev_private;
172 /* Disable compression */
173 dpfc_ctl = I915_READ(DPFC_CONTROL);
174 if (dpfc_ctl & DPFC_CTL_EN) {
175 dpfc_ctl &= ~DPFC_CTL_EN;
176 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
178 DRM_DEBUG_KMS("disabled FBC\n");
182 static bool g4x_fbc_enabled(struct drm_device *dev)
184 struct drm_i915_private *dev_priv = dev->dev_private;
186 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
189 static void sandybridge_blit_fbc_update(struct drm_device *dev)
191 struct drm_i915_private *dev_priv = dev->dev_private;
194 /* Make sure blitter notifies FBC of writes */
196 /* Blitter is part of Media powerwell on VLV. No impact of
197 * his param in other platforms for now */
198 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
200 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
201 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
202 GEN6_BLITTER_LOCK_SHIFT;
203 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
204 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
205 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
206 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
207 GEN6_BLITTER_LOCK_SHIFT);
208 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
209 POSTING_READ(GEN6_BLITTER_ECOSKPD);
211 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
214 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
216 struct drm_device *dev = crtc->dev;
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 struct drm_framebuffer *fb = crtc->fb;
219 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
220 struct drm_i915_gem_object *obj = intel_fb->obj;
221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
222 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
223 unsigned long stall_watermark = 200;
226 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
227 dpfc_ctl &= DPFC_RESERVED;
228 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
229 /* Set persistent mode for front-buffer rendering, ala X. */
230 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
231 dpfc_ctl |= DPFC_CTL_FENCE_EN;
233 dpfc_ctl |= obj->fence_reg;
234 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
236 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
237 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
238 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
254 static void ironlake_disable_fbc(struct drm_device *dev)
256 struct drm_i915_private *dev_priv = dev->dev_private;
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265 DRM_DEBUG_KMS("disabled FBC\n");
269 static bool ironlake_fbc_enabled(struct drm_device *dev)
271 struct drm_i915_private *dev_priv = dev->dev_private;
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
276 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 struct drm_framebuffer *fb = crtc->fb;
281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
285 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
287 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
288 IVB_DPFC_CTL_FENCE_EN |
289 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
291 if (IS_IVYBRIDGE(dev)) {
292 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
293 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
295 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
296 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
297 HSW_BYPASS_FBC_QUEUE);
300 I915_WRITE(SNB_DPFC_CTL_SA,
301 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
302 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304 sandybridge_blit_fbc_update(dev);
306 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
309 bool intel_fbc_enabled(struct drm_device *dev)
311 struct drm_i915_private *dev_priv = dev->dev_private;
313 if (!dev_priv->display.fbc_enabled)
316 return dev_priv->display.fbc_enabled(dev);
319 static void intel_fbc_work_fn(struct work_struct *__work)
321 struct intel_fbc_work *work =
322 container_of(to_delayed_work(__work),
323 struct intel_fbc_work, work);
324 struct drm_device *dev = work->crtc->dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
327 mutex_lock(&dev->struct_mutex);
328 if (work == dev_priv->fbc.fbc_work) {
329 /* Double check that we haven't switched fb without cancelling
332 if (work->crtc->fb == work->fb) {
333 dev_priv->display.enable_fbc(work->crtc,
336 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
338 dev_priv->fbc.y = work->crtc->y;
341 dev_priv->fbc.fbc_work = NULL;
343 mutex_unlock(&dev->struct_mutex);
348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
350 if (dev_priv->fbc.fbc_work == NULL)
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc.fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
359 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv->fbc.fbc_work);
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
368 dev_priv->fbc.fbc_work = NULL;
371 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
377 if (!dev_priv->display.enable_fbc)
380 intel_cancel_fbc_work(dev_priv);
382 work = kzalloc(sizeof(*work), GFP_KERNEL);
384 DRM_ERROR("Failed to allocate FBC work structure\n");
385 dev_priv->display.enable_fbc(crtc, interval);
391 work->interval = interval;
392 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
394 dev_priv->fbc.fbc_work = work;
396 /* Delay the actual enabling to let pageflipping cease and the
397 * display to settle before starting the compression. Note that
398 * this delay also serves a second purpose: it allows for a
399 * vblank to pass after disabling the FBC before we attempt
400 * to modify the control registers.
402 * A more complicated solution would involve tracking vblanks
403 * following the termination of the page-flipping sequence
404 * and indeed performing the enable as a co-routine and not
405 * waiting synchronously upon the vblank.
407 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
409 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
412 void intel_disable_fbc(struct drm_device *dev)
414 struct drm_i915_private *dev_priv = dev->dev_private;
416 intel_cancel_fbc_work(dev_priv);
418 if (!dev_priv->display.disable_fbc)
421 dev_priv->display.disable_fbc(dev);
422 dev_priv->fbc.plane = -1;
425 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
426 enum no_fbc_reason reason)
428 if (dev_priv->fbc.no_fbc_reason == reason)
431 dev_priv->fbc.no_fbc_reason = reason;
436 * intel_update_fbc - enable/disable FBC as needed
437 * @dev: the drm_device
439 * Set up the framebuffer compression hardware at mode set time. We
440 * enable it if possible:
441 * - plane A only (on pre-965)
442 * - no pixel mulitply/line duplication
443 * - no alpha buffer discard
445 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
447 * We can't assume that any compression will take place (worst case),
448 * so the compressed buffer has to be the same size as the uncompressed
449 * one. It also must reside (along with the line length buffer) in
452 * We need to enable/disable FBC on a global basis.
454 void intel_update_fbc(struct drm_device *dev)
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 struct drm_crtc *crtc = NULL, *tmp_crtc;
458 struct intel_crtc *intel_crtc;
459 struct drm_framebuffer *fb;
460 struct intel_framebuffer *intel_fb;
461 struct drm_i915_gem_object *obj;
462 const struct drm_display_mode *adjusted_mode;
463 unsigned int max_width, max_height;
465 if (!I915_HAS_FBC(dev)) {
466 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
470 if (!i915_powersave) {
471 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
472 DRM_DEBUG_KMS("fbc disabled per module param\n");
477 * If FBC is already on, we just have to verify that we can
478 * keep it that way...
479 * Need to disable if:
480 * - more than one pipe is active
481 * - changing FBC params (stride, fence, mode)
482 * - new fb is too large to fit in compressed buffer
483 * - going to an unsupported config (interlace, pixel multiply, etc.)
485 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
486 if (intel_crtc_active(tmp_crtc) &&
487 to_intel_crtc(tmp_crtc)->primary_enabled) {
489 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
490 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
497 if (!crtc || crtc->fb == NULL) {
498 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
499 DRM_DEBUG_KMS("no output, disabling\n");
503 intel_crtc = to_intel_crtc(crtc);
505 intel_fb = to_intel_framebuffer(fb);
507 adjusted_mode = &intel_crtc->config.adjusted_mode;
509 if (i915_enable_fbc < 0 &&
510 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
511 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
512 DRM_DEBUG_KMS("disabled per chip default\n");
515 if (!i915_enable_fbc) {
516 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
517 DRM_DEBUG_KMS("fbc disabled per module param\n");
520 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
521 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
522 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
523 DRM_DEBUG_KMS("mode incompatible with compression, "
528 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
535 if (intel_crtc->config.pipe_src_w > max_width ||
536 intel_crtc->config.pipe_src_h > max_height) {
537 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
538 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
541 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
542 intel_crtc->plane != PLANE_A) {
543 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
544 DRM_DEBUG_KMS("plane not A, disabling compression\n");
548 /* The use of a CPU fence is mandatory in order to detect writes
549 * by the CPU to the scanout and trigger updates to the FBC.
551 if (obj->tiling_mode != I915_TILING_X ||
552 obj->fence_reg == I915_FENCE_REG_NONE) {
553 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
554 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
558 /* If the kernel debugger is active, always disable compression */
562 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
563 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
564 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
568 /* If the scanout has not changed, don't modify the FBC settings.
569 * Note that we make the fundamental assumption that the fb->obj
570 * cannot be unpinned (and have its GTT offset and fence revoked)
571 * without first being decoupled from the scanout and FBC disabled.
573 if (dev_priv->fbc.plane == intel_crtc->plane &&
574 dev_priv->fbc.fb_id == fb->base.id &&
575 dev_priv->fbc.y == crtc->y)
578 if (intel_fbc_enabled(dev)) {
579 /* We update FBC along two paths, after changing fb/crtc
580 * configuration (modeswitching) and after page-flipping
581 * finishes. For the latter, we know that not only did
582 * we disable the FBC at the start of the page-flip
583 * sequence, but also more than one vblank has passed.
585 * For the former case of modeswitching, it is possible
586 * to switch between two FBC valid configurations
587 * instantaneously so we do need to disable the FBC
588 * before we can modify its control registers. We also
589 * have to wait for the next vblank for that to take
590 * effect. However, since we delay enabling FBC we can
591 * assume that a vblank has passed since disabling and
592 * that we can safely alter the registers in the deferred
595 * In the scenario that we go from a valid to invalid
596 * and then back to valid FBC configuration we have
597 * no strict enforcement that a vblank occurred since
598 * disabling the FBC. However, along all current pipe
599 * disabling paths we do need to wait for a vblank at
600 * some point. And we wait before enabling FBC anyway.
602 DRM_DEBUG_KMS("disabling active FBC for update\n");
603 intel_disable_fbc(dev);
606 intel_enable_fbc(crtc, 500);
607 dev_priv->fbc.no_fbc_reason = FBC_OK;
611 /* Multiple disables should be harmless */
612 if (intel_fbc_enabled(dev)) {
613 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
614 intel_disable_fbc(dev);
616 i915_gem_stolen_cleanup_compression(dev);
619 static void i915_pineview_get_mem_freq(struct drm_device *dev)
621 drm_i915_private_t *dev_priv = dev->dev_private;
624 tmp = I915_READ(CLKCFG);
626 switch (tmp & CLKCFG_FSB_MASK) {
628 dev_priv->fsb_freq = 533; /* 133*4 */
631 dev_priv->fsb_freq = 800; /* 200*4 */
634 dev_priv->fsb_freq = 667; /* 167*4 */
637 dev_priv->fsb_freq = 400; /* 100*4 */
641 switch (tmp & CLKCFG_MEM_MASK) {
643 dev_priv->mem_freq = 533;
646 dev_priv->mem_freq = 667;
649 dev_priv->mem_freq = 800;
653 /* detect pineview DDR3 setting */
654 tmp = I915_READ(CSHRDDR3CTL);
655 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
658 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
660 drm_i915_private_t *dev_priv = dev->dev_private;
663 ddrpll = I915_READ16(DDRMPLL1);
664 csipll = I915_READ16(CSIPLL0);
666 switch (ddrpll & 0xff) {
668 dev_priv->mem_freq = 800;
671 dev_priv->mem_freq = 1066;
674 dev_priv->mem_freq = 1333;
677 dev_priv->mem_freq = 1600;
680 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
682 dev_priv->mem_freq = 0;
686 dev_priv->ips.r_t = dev_priv->mem_freq;
688 switch (csipll & 0x3ff) {
690 dev_priv->fsb_freq = 3200;
693 dev_priv->fsb_freq = 3733;
696 dev_priv->fsb_freq = 4266;
699 dev_priv->fsb_freq = 4800;
702 dev_priv->fsb_freq = 5333;
705 dev_priv->fsb_freq = 5866;
708 dev_priv->fsb_freq = 6400;
711 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
713 dev_priv->fsb_freq = 0;
717 if (dev_priv->fsb_freq == 3200) {
718 dev_priv->ips.c_m = 0;
719 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
720 dev_priv->ips.c_m = 1;
722 dev_priv->ips.c_m = 2;
726 static const struct cxsr_latency cxsr_latency_table[] = {
727 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
728 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
729 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
730 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
731 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
733 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
734 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
735 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
736 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
737 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
739 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
740 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
741 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
742 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
743 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
745 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
746 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
747 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
748 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
749 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
751 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
752 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
753 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
754 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
755 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
757 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
758 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
759 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
760 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
761 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
764 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
769 const struct cxsr_latency *latency;
772 if (fsb == 0 || mem == 0)
775 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
776 latency = &cxsr_latency_table[i];
777 if (is_desktop == latency->is_desktop &&
778 is_ddr3 == latency->is_ddr3 &&
779 fsb == latency->fsb_freq && mem == latency->mem_freq)
783 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
788 static void pineview_disable_cxsr(struct drm_device *dev)
790 struct drm_i915_private *dev_priv = dev->dev_private;
792 /* deactivate cxsr */
793 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
797 * Latency for FIFO fetches is dependent on several factors:
798 * - memory configuration (speed, channels)
800 * - current MCH state
801 * It can be fairly high in some situations, so here we assume a fairly
802 * pessimal value. It's a tradeoff between extra memory fetches (if we
803 * set this value too high, the FIFO will fetch frequently to stay full)
804 * and power consumption (set it too low to save power and we might see
805 * FIFO underruns and display "flicker").
807 * A value of 5us seems to be a good balance; safe for very low end
808 * platforms but not overly aggressive on lower latency configs.
810 static const int latency_ns = 5000;
812 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 uint32_t dsparb = I915_READ(DSPARB);
818 size = dsparb & 0x7f;
820 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
822 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
823 plane ? "B" : "A", size);
828 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
830 struct drm_i915_private *dev_priv = dev->dev_private;
831 uint32_t dsparb = I915_READ(DSPARB);
834 size = dsparb & 0x1ff;
836 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
837 size >>= 1; /* Convert to cachelines */
839 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
840 plane ? "B" : "A", size);
845 static int i845_get_fifo_size(struct drm_device *dev, int plane)
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 uint32_t dsparb = I915_READ(DSPARB);
851 size = dsparb & 0x7f;
852 size >>= 2; /* Convert to cachelines */
854 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
861 static int i830_get_fifo_size(struct drm_device *dev, int plane)
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 uint32_t dsparb = I915_READ(DSPARB);
867 size = dsparb & 0x7f;
868 size >>= 1; /* Convert to cachelines */
870 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
871 plane ? "B" : "A", size);
876 /* Pineview has different values for various configs */
877 static const struct intel_watermark_params pineview_display_wm = {
878 PINEVIEW_DISPLAY_FIFO,
882 PINEVIEW_FIFO_LINE_SIZE
884 static const struct intel_watermark_params pineview_display_hplloff_wm = {
885 PINEVIEW_DISPLAY_FIFO,
887 PINEVIEW_DFT_HPLLOFF_WM,
889 PINEVIEW_FIFO_LINE_SIZE
891 static const struct intel_watermark_params pineview_cursor_wm = {
892 PINEVIEW_CURSOR_FIFO,
893 PINEVIEW_CURSOR_MAX_WM,
894 PINEVIEW_CURSOR_DFT_WM,
895 PINEVIEW_CURSOR_GUARD_WM,
896 PINEVIEW_FIFO_LINE_SIZE,
898 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
899 PINEVIEW_CURSOR_FIFO,
900 PINEVIEW_CURSOR_MAX_WM,
901 PINEVIEW_CURSOR_DFT_WM,
902 PINEVIEW_CURSOR_GUARD_WM,
903 PINEVIEW_FIFO_LINE_SIZE
905 static const struct intel_watermark_params g4x_wm_info = {
912 static const struct intel_watermark_params g4x_cursor_wm_info = {
919 static const struct intel_watermark_params valleyview_wm_info = {
920 VALLEYVIEW_FIFO_SIZE,
926 static const struct intel_watermark_params valleyview_cursor_wm_info = {
928 VALLEYVIEW_CURSOR_MAX_WM,
933 static const struct intel_watermark_params i965_cursor_wm_info = {
940 static const struct intel_watermark_params i945_wm_info = {
947 static const struct intel_watermark_params i915_wm_info = {
954 static const struct intel_watermark_params i855_wm_info = {
961 static const struct intel_watermark_params i830_wm_info = {
969 static const struct intel_watermark_params ironlake_display_wm_info = {
976 static const struct intel_watermark_params ironlake_cursor_wm_info = {
983 static const struct intel_watermark_params ironlake_display_srwm_info = {
985 ILK_DISPLAY_MAX_SRWM,
986 ILK_DISPLAY_DFT_SRWM,
990 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
998 static const struct intel_watermark_params sandybridge_display_wm_info = {
1005 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1012 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1013 SNB_DISPLAY_SR_FIFO,
1014 SNB_DISPLAY_MAX_SRWM,
1015 SNB_DISPLAY_DFT_SRWM,
1019 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1021 SNB_CURSOR_MAX_SRWM,
1022 SNB_CURSOR_DFT_SRWM,
1029 * intel_calculate_wm - calculate watermark level
1030 * @clock_in_khz: pixel clock
1031 * @wm: chip FIFO params
1032 * @pixel_size: display pixel size
1033 * @latency_ns: memory latency for the platform
1035 * Calculate the watermark level (the level at which the display plane will
1036 * start fetching from memory again). Each chip has a different display
1037 * FIFO size and allocation, so the caller needs to figure that out and pass
1038 * in the correct intel_watermark_params structure.
1040 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1041 * on the pixel size. When it reaches the watermark level, it'll start
1042 * fetching FIFO line sized based chunks from memory until the FIFO fills
1043 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1044 * will occur, and a display engine hang could result.
1046 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1047 const struct intel_watermark_params *wm,
1050 unsigned long latency_ns)
1052 long entries_required, wm_size;
1055 * Note: we need to make sure we don't overflow for various clock &
1057 * clocks go from a few thousand to several hundred thousand.
1058 * latency is usually a few thousand
1060 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1062 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1064 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1066 wm_size = fifo_size - (entries_required + wm->guard_size);
1068 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1070 /* Don't promote wm_size to unsigned... */
1071 if (wm_size > (long)wm->max_wm)
1072 wm_size = wm->max_wm;
1074 wm_size = wm->default_wm;
1078 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1080 struct drm_crtc *crtc, *enabled = NULL;
1082 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1083 if (intel_crtc_active(crtc)) {
1093 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1095 struct drm_device *dev = unused_crtc->dev;
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 struct drm_crtc *crtc;
1098 const struct cxsr_latency *latency;
1102 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1103 dev_priv->fsb_freq, dev_priv->mem_freq);
1105 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1106 pineview_disable_cxsr(dev);
1110 crtc = single_enabled_crtc(dev);
1112 const struct drm_display_mode *adjusted_mode;
1113 int pixel_size = crtc->fb->bits_per_pixel / 8;
1116 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1117 clock = adjusted_mode->crtc_clock;
1120 wm = intel_calculate_wm(clock, &pineview_display_wm,
1121 pineview_display_wm.fifo_size,
1122 pixel_size, latency->display_sr);
1123 reg = I915_READ(DSPFW1);
1124 reg &= ~DSPFW_SR_MASK;
1125 reg |= wm << DSPFW_SR_SHIFT;
1126 I915_WRITE(DSPFW1, reg);
1127 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1130 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1131 pineview_display_wm.fifo_size,
1132 pixel_size, latency->cursor_sr);
1133 reg = I915_READ(DSPFW3);
1134 reg &= ~DSPFW_CURSOR_SR_MASK;
1135 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1136 I915_WRITE(DSPFW3, reg);
1138 /* Display HPLL off SR */
1139 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1140 pineview_display_hplloff_wm.fifo_size,
1141 pixel_size, latency->display_hpll_disable);
1142 reg = I915_READ(DSPFW3);
1143 reg &= ~DSPFW_HPLL_SR_MASK;
1144 reg |= wm & DSPFW_HPLL_SR_MASK;
1145 I915_WRITE(DSPFW3, reg);
1147 /* cursor HPLL off SR */
1148 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1149 pineview_display_hplloff_wm.fifo_size,
1150 pixel_size, latency->cursor_hpll_disable);
1151 reg = I915_READ(DSPFW3);
1152 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1153 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1154 I915_WRITE(DSPFW3, reg);
1155 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1159 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1160 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1162 pineview_disable_cxsr(dev);
1163 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1167 static bool g4x_compute_wm0(struct drm_device *dev,
1169 const struct intel_watermark_params *display,
1170 int display_latency_ns,
1171 const struct intel_watermark_params *cursor,
1172 int cursor_latency_ns,
1176 struct drm_crtc *crtc;
1177 const struct drm_display_mode *adjusted_mode;
1178 int htotal, hdisplay, clock, pixel_size;
1179 int line_time_us, line_count;
1180 int entries, tlb_miss;
1182 crtc = intel_get_crtc_for_plane(dev, plane);
1183 if (!intel_crtc_active(crtc)) {
1184 *cursor_wm = cursor->guard_size;
1185 *plane_wm = display->guard_size;
1189 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1190 clock = adjusted_mode->crtc_clock;
1191 htotal = adjusted_mode->crtc_htotal;
1192 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1193 pixel_size = crtc->fb->bits_per_pixel / 8;
1195 /* Use the small buffer method to calculate plane watermark */
1196 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1197 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1199 entries += tlb_miss;
1200 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1201 *plane_wm = entries + display->guard_size;
1202 if (*plane_wm > (int)display->max_wm)
1203 *plane_wm = display->max_wm;
1205 /* Use the large buffer method to calculate cursor watermark */
1206 line_time_us = ((htotal * 1000) / clock);
1207 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1208 entries = line_count * 64 * pixel_size;
1209 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1211 entries += tlb_miss;
1212 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1213 *cursor_wm = entries + cursor->guard_size;
1214 if (*cursor_wm > (int)cursor->max_wm)
1215 *cursor_wm = (int)cursor->max_wm;
1221 * Check the wm result.
1223 * If any calculated watermark values is larger than the maximum value that
1224 * can be programmed into the associated watermark register, that watermark
1227 static bool g4x_check_srwm(struct drm_device *dev,
1228 int display_wm, int cursor_wm,
1229 const struct intel_watermark_params *display,
1230 const struct intel_watermark_params *cursor)
1232 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1233 display_wm, cursor_wm);
1235 if (display_wm > display->max_wm) {
1236 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1237 display_wm, display->max_wm);
1241 if (cursor_wm > cursor->max_wm) {
1242 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1243 cursor_wm, cursor->max_wm);
1247 if (!(display_wm || cursor_wm)) {
1248 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1255 static bool g4x_compute_srwm(struct drm_device *dev,
1258 const struct intel_watermark_params *display,
1259 const struct intel_watermark_params *cursor,
1260 int *display_wm, int *cursor_wm)
1262 struct drm_crtc *crtc;
1263 const struct drm_display_mode *adjusted_mode;
1264 int hdisplay, htotal, pixel_size, clock;
1265 unsigned long line_time_us;
1266 int line_count, line_size;
1271 *display_wm = *cursor_wm = 0;
1275 crtc = intel_get_crtc_for_plane(dev, plane);
1276 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1277 clock = adjusted_mode->crtc_clock;
1278 htotal = adjusted_mode->crtc_htotal;
1279 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1280 pixel_size = crtc->fb->bits_per_pixel / 8;
1282 line_time_us = (htotal * 1000) / clock;
1283 line_count = (latency_ns / line_time_us + 1000) / 1000;
1284 line_size = hdisplay * pixel_size;
1286 /* Use the minimum of the small and large buffer method for primary */
1287 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1288 large = line_count * line_size;
1290 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1291 *display_wm = entries + display->guard_size;
1293 /* calculate the self-refresh watermark for display cursor */
1294 entries = line_count * pixel_size * 64;
1295 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1296 *cursor_wm = entries + cursor->guard_size;
1298 return g4x_check_srwm(dev,
1299 *display_wm, *cursor_wm,
1303 static bool vlv_compute_drain_latency(struct drm_device *dev,
1305 int *plane_prec_mult,
1307 int *cursor_prec_mult,
1310 struct drm_crtc *crtc;
1311 int clock, pixel_size;
1314 crtc = intel_get_crtc_for_plane(dev, plane);
1315 if (!intel_crtc_active(crtc))
1318 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1319 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1321 entries = (clock / 1000) * pixel_size;
1322 *plane_prec_mult = (entries > 256) ?
1323 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1324 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1327 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1328 *cursor_prec_mult = (entries > 256) ?
1329 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1330 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1336 * Update drain latency registers of memory arbiter
1338 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1339 * to be programmed. Each plane has a drain latency multiplier and a drain
1343 static void vlv_update_drain_latency(struct drm_device *dev)
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1347 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1348 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1351 /* For plane A, Cursor A */
1352 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1353 &cursor_prec_mult, &cursora_dl)) {
1354 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1355 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1356 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1357 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1359 I915_WRITE(VLV_DDL1, cursora_prec |
1360 (cursora_dl << DDL_CURSORA_SHIFT) |
1361 planea_prec | planea_dl);
1364 /* For plane B, Cursor B */
1365 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1366 &cursor_prec_mult, &cursorb_dl)) {
1367 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1368 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1369 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1370 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1372 I915_WRITE(VLV_DDL2, cursorb_prec |
1373 (cursorb_dl << DDL_CURSORB_SHIFT) |
1374 planeb_prec | planeb_dl);
1378 #define single_plane_enabled(mask) is_power_of_2(mask)
1380 static void valleyview_update_wm(struct drm_crtc *crtc)
1382 struct drm_device *dev = crtc->dev;
1383 static const int sr_latency_ns = 12000;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386 int plane_sr, cursor_sr;
1387 int ignore_plane_sr, ignore_cursor_sr;
1388 unsigned int enabled = 0;
1390 vlv_update_drain_latency(dev);
1392 if (g4x_compute_wm0(dev, PIPE_A,
1393 &valleyview_wm_info, latency_ns,
1394 &valleyview_cursor_wm_info, latency_ns,
1395 &planea_wm, &cursora_wm))
1396 enabled |= 1 << PIPE_A;
1398 if (g4x_compute_wm0(dev, PIPE_B,
1399 &valleyview_wm_info, latency_ns,
1400 &valleyview_cursor_wm_info, latency_ns,
1401 &planeb_wm, &cursorb_wm))
1402 enabled |= 1 << PIPE_B;
1404 if (single_plane_enabled(enabled) &&
1405 g4x_compute_srwm(dev, ffs(enabled) - 1,
1407 &valleyview_wm_info,
1408 &valleyview_cursor_wm_info,
1409 &plane_sr, &ignore_cursor_sr) &&
1410 g4x_compute_srwm(dev, ffs(enabled) - 1,
1412 &valleyview_wm_info,
1413 &valleyview_cursor_wm_info,
1414 &ignore_plane_sr, &cursor_sr)) {
1415 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1417 I915_WRITE(FW_BLC_SELF_VLV,
1418 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1419 plane_sr = cursor_sr = 0;
1422 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1423 planea_wm, cursora_wm,
1424 planeb_wm, cursorb_wm,
1425 plane_sr, cursor_sr);
1428 (plane_sr << DSPFW_SR_SHIFT) |
1429 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1430 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1433 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1434 (cursora_wm << DSPFW_CURSORA_SHIFT));
1436 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1437 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1440 static void g4x_update_wm(struct drm_crtc *crtc)
1442 struct drm_device *dev = crtc->dev;
1443 static const int sr_latency_ns = 12000;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1446 int plane_sr, cursor_sr;
1447 unsigned int enabled = 0;
1449 if (g4x_compute_wm0(dev, PIPE_A,
1450 &g4x_wm_info, latency_ns,
1451 &g4x_cursor_wm_info, latency_ns,
1452 &planea_wm, &cursora_wm))
1453 enabled |= 1 << PIPE_A;
1455 if (g4x_compute_wm0(dev, PIPE_B,
1456 &g4x_wm_info, latency_ns,
1457 &g4x_cursor_wm_info, latency_ns,
1458 &planeb_wm, &cursorb_wm))
1459 enabled |= 1 << PIPE_B;
1461 if (single_plane_enabled(enabled) &&
1462 g4x_compute_srwm(dev, ffs(enabled) - 1,
1465 &g4x_cursor_wm_info,
1466 &plane_sr, &cursor_sr)) {
1467 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1469 I915_WRITE(FW_BLC_SELF,
1470 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1471 plane_sr = cursor_sr = 0;
1474 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1475 planea_wm, cursora_wm,
1476 planeb_wm, cursorb_wm,
1477 plane_sr, cursor_sr);
1480 (plane_sr << DSPFW_SR_SHIFT) |
1481 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1482 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1485 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1486 (cursora_wm << DSPFW_CURSORA_SHIFT));
1487 /* HPLL off in SR has some issues on G4x... disable it */
1489 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1490 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1493 static void i965_update_wm(struct drm_crtc *unused_crtc)
1495 struct drm_device *dev = unused_crtc->dev;
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497 struct drm_crtc *crtc;
1501 /* Calc sr entries for one plane configs */
1502 crtc = single_enabled_crtc(dev);
1504 /* self-refresh has much higher latency */
1505 static const int sr_latency_ns = 12000;
1506 const struct drm_display_mode *adjusted_mode =
1507 &to_intel_crtc(crtc)->config.adjusted_mode;
1508 int clock = adjusted_mode->crtc_clock;
1509 int htotal = adjusted_mode->crtc_htotal;
1510 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1511 int pixel_size = crtc->fb->bits_per_pixel / 8;
1512 unsigned long line_time_us;
1515 line_time_us = ((htotal * 1000) / clock);
1517 /* Use ns/us then divide to preserve precision */
1518 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1519 pixel_size * hdisplay;
1520 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1521 srwm = I965_FIFO_SIZE - entries;
1525 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1528 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1530 entries = DIV_ROUND_UP(entries,
1531 i965_cursor_wm_info.cacheline_size);
1532 cursor_sr = i965_cursor_wm_info.fifo_size -
1533 (entries + i965_cursor_wm_info.guard_size);
1535 if (cursor_sr > i965_cursor_wm_info.max_wm)
1536 cursor_sr = i965_cursor_wm_info.max_wm;
1538 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1539 "cursor %d\n", srwm, cursor_sr);
1541 if (IS_CRESTLINE(dev))
1542 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1544 /* Turn off self refresh if both pipes are enabled */
1545 if (IS_CRESTLINE(dev))
1546 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1550 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1553 /* 965 has limitations... */
1554 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1555 (8 << 16) | (8 << 8) | (8 << 0));
1556 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1557 /* update cursor SR watermark */
1558 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1561 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1563 struct drm_device *dev = unused_crtc->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 const struct intel_watermark_params *wm_info;
1570 int planea_wm, planeb_wm;
1571 struct drm_crtc *crtc, *enabled = NULL;
1574 wm_info = &i945_wm_info;
1575 else if (!IS_GEN2(dev))
1576 wm_info = &i915_wm_info;
1578 wm_info = &i855_wm_info;
1580 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1581 crtc = intel_get_crtc_for_plane(dev, 0);
1582 if (intel_crtc_active(crtc)) {
1583 const struct drm_display_mode *adjusted_mode;
1584 int cpp = crtc->fb->bits_per_pixel / 8;
1588 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1589 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1590 wm_info, fifo_size, cpp,
1594 planea_wm = fifo_size - wm_info->guard_size;
1596 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1597 crtc = intel_get_crtc_for_plane(dev, 1);
1598 if (intel_crtc_active(crtc)) {
1599 const struct drm_display_mode *adjusted_mode;
1600 int cpp = crtc->fb->bits_per_pixel / 8;
1604 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1605 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1606 wm_info, fifo_size, cpp,
1608 if (enabled == NULL)
1613 planeb_wm = fifo_size - wm_info->guard_size;
1615 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1618 * Overlay gets an aggressive default since video jitter is bad.
1622 /* Play safe and disable self-refresh before adjusting watermarks. */
1623 if (IS_I945G(dev) || IS_I945GM(dev))
1624 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1625 else if (IS_I915GM(dev))
1626 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1628 /* Calc sr entries for one plane configs */
1629 if (HAS_FW_BLC(dev) && enabled) {
1630 /* self-refresh has much higher latency */
1631 static const int sr_latency_ns = 6000;
1632 const struct drm_display_mode *adjusted_mode =
1633 &to_intel_crtc(enabled)->config.adjusted_mode;
1634 int clock = adjusted_mode->crtc_clock;
1635 int htotal = adjusted_mode->crtc_htotal;
1636 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1637 int pixel_size = enabled->fb->bits_per_pixel / 8;
1638 unsigned long line_time_us;
1641 line_time_us = (htotal * 1000) / clock;
1643 /* Use ns/us then divide to preserve precision */
1644 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1645 pixel_size * hdisplay;
1646 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1647 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1648 srwm = wm_info->fifo_size - entries;
1652 if (IS_I945G(dev) || IS_I945GM(dev))
1653 I915_WRITE(FW_BLC_SELF,
1654 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1655 else if (IS_I915GM(dev))
1656 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1659 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1660 planea_wm, planeb_wm, cwm, srwm);
1662 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1663 fwater_hi = (cwm & 0x1f);
1665 /* Set request length to 8 cachelines per fetch */
1666 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1667 fwater_hi = fwater_hi | (1 << 8);
1669 I915_WRITE(FW_BLC, fwater_lo);
1670 I915_WRITE(FW_BLC2, fwater_hi);
1672 if (HAS_FW_BLC(dev)) {
1674 if (IS_I945G(dev) || IS_I945GM(dev))
1675 I915_WRITE(FW_BLC_SELF,
1676 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1677 else if (IS_I915GM(dev))
1678 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1679 DRM_DEBUG_KMS("memory self refresh enabled\n");
1681 DRM_DEBUG_KMS("memory self refresh disabled\n");
1685 static void i830_update_wm(struct drm_crtc *unused_crtc)
1687 struct drm_device *dev = unused_crtc->dev;
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689 struct drm_crtc *crtc;
1690 const struct drm_display_mode *adjusted_mode;
1694 crtc = single_enabled_crtc(dev);
1698 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1699 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1701 dev_priv->display.get_fifo_size(dev, 0),
1703 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1704 fwater_lo |= (3<<8) | planea_wm;
1706 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1708 I915_WRITE(FW_BLC, fwater_lo);
1712 * Check the wm result.
1714 * If any calculated watermark values is larger than the maximum value that
1715 * can be programmed into the associated watermark register, that watermark
1718 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1719 int fbc_wm, int display_wm, int cursor_wm,
1720 const struct intel_watermark_params *display,
1721 const struct intel_watermark_params *cursor)
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1725 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1726 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1728 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1729 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1730 fbc_wm, SNB_FBC_MAX_SRWM, level);
1732 /* fbc has it's own way to disable FBC WM */
1733 I915_WRITE(DISP_ARB_CTL,
1734 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1736 } else if (INTEL_INFO(dev)->gen >= 6) {
1737 /* enable FBC WM (except on ILK, where it must remain off) */
1738 I915_WRITE(DISP_ARB_CTL,
1739 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1742 if (display_wm > display->max_wm) {
1743 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1744 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1748 if (cursor_wm > cursor->max_wm) {
1749 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1750 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1754 if (!(fbc_wm || display_wm || cursor_wm)) {
1755 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1763 * Compute watermark values of WM[1-3],
1765 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1767 const struct intel_watermark_params *display,
1768 const struct intel_watermark_params *cursor,
1769 int *fbc_wm, int *display_wm, int *cursor_wm)
1771 struct drm_crtc *crtc;
1772 const struct drm_display_mode *adjusted_mode;
1773 unsigned long line_time_us;
1774 int hdisplay, htotal, pixel_size, clock;
1775 int line_count, line_size;
1780 *fbc_wm = *display_wm = *cursor_wm = 0;
1784 crtc = intel_get_crtc_for_plane(dev, plane);
1785 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1786 clock = adjusted_mode->crtc_clock;
1787 htotal = adjusted_mode->crtc_htotal;
1788 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1789 pixel_size = crtc->fb->bits_per_pixel / 8;
1791 line_time_us = (htotal * 1000) / clock;
1792 line_count = (latency_ns / line_time_us + 1000) / 1000;
1793 line_size = hdisplay * pixel_size;
1795 /* Use the minimum of the small and large buffer method for primary */
1796 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1797 large = line_count * line_size;
1799 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1800 *display_wm = entries + display->guard_size;
1804 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1806 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1808 /* calculate the self-refresh watermark for display cursor */
1809 entries = line_count * pixel_size * 64;
1810 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1811 *cursor_wm = entries + cursor->guard_size;
1813 return ironlake_check_srwm(dev, level,
1814 *fbc_wm, *display_wm, *cursor_wm,
1818 static void ironlake_update_wm(struct drm_crtc *crtc)
1820 struct drm_device *dev = crtc->dev;
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 int fbc_wm, plane_wm, cursor_wm;
1823 unsigned int enabled;
1826 if (g4x_compute_wm0(dev, PIPE_A,
1827 &ironlake_display_wm_info,
1828 dev_priv->wm.pri_latency[0] * 100,
1829 &ironlake_cursor_wm_info,
1830 dev_priv->wm.cur_latency[0] * 100,
1831 &plane_wm, &cursor_wm)) {
1832 I915_WRITE(WM0_PIPEA_ILK,
1833 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1834 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1835 " plane %d, " "cursor: %d\n",
1836 plane_wm, cursor_wm);
1837 enabled |= 1 << PIPE_A;
1840 if (g4x_compute_wm0(dev, PIPE_B,
1841 &ironlake_display_wm_info,
1842 dev_priv->wm.pri_latency[0] * 100,
1843 &ironlake_cursor_wm_info,
1844 dev_priv->wm.cur_latency[0] * 100,
1845 &plane_wm, &cursor_wm)) {
1846 I915_WRITE(WM0_PIPEB_ILK,
1847 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1848 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1849 " plane %d, cursor: %d\n",
1850 plane_wm, cursor_wm);
1851 enabled |= 1 << PIPE_B;
1855 * Calculate and update the self-refresh watermark only when one
1856 * display plane is used.
1858 I915_WRITE(WM3_LP_ILK, 0);
1859 I915_WRITE(WM2_LP_ILK, 0);
1860 I915_WRITE(WM1_LP_ILK, 0);
1862 if (!single_plane_enabled(enabled))
1864 enabled = ffs(enabled) - 1;
1867 if (!ironlake_compute_srwm(dev, 1, enabled,
1868 dev_priv->wm.pri_latency[1] * 500,
1869 &ironlake_display_srwm_info,
1870 &ironlake_cursor_srwm_info,
1871 &fbc_wm, &plane_wm, &cursor_wm))
1874 I915_WRITE(WM1_LP_ILK,
1876 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1877 (fbc_wm << WM1_LP_FBC_SHIFT) |
1878 (plane_wm << WM1_LP_SR_SHIFT) |
1882 if (!ironlake_compute_srwm(dev, 2, enabled,
1883 dev_priv->wm.pri_latency[2] * 500,
1884 &ironlake_display_srwm_info,
1885 &ironlake_cursor_srwm_info,
1886 &fbc_wm, &plane_wm, &cursor_wm))
1889 I915_WRITE(WM2_LP_ILK,
1891 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1892 (fbc_wm << WM1_LP_FBC_SHIFT) |
1893 (plane_wm << WM1_LP_SR_SHIFT) |
1897 * WM3 is unsupported on ILK, probably because we don't have latency
1898 * data for that power state
1902 static void sandybridge_update_wm(struct drm_crtc *crtc)
1904 struct drm_device *dev = crtc->dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1908 int fbc_wm, plane_wm, cursor_wm;
1909 unsigned int enabled;
1912 if (g4x_compute_wm0(dev, PIPE_A,
1913 &sandybridge_display_wm_info, latency,
1914 &sandybridge_cursor_wm_info, latency,
1915 &plane_wm, &cursor_wm)) {
1916 val = I915_READ(WM0_PIPEA_ILK);
1917 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1918 I915_WRITE(WM0_PIPEA_ILK, val |
1919 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1920 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1921 " plane %d, " "cursor: %d\n",
1922 plane_wm, cursor_wm);
1923 enabled |= 1 << PIPE_A;
1926 if (g4x_compute_wm0(dev, PIPE_B,
1927 &sandybridge_display_wm_info, latency,
1928 &sandybridge_cursor_wm_info, latency,
1929 &plane_wm, &cursor_wm)) {
1930 val = I915_READ(WM0_PIPEB_ILK);
1931 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1932 I915_WRITE(WM0_PIPEB_ILK, val |
1933 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1934 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1935 " plane %d, cursor: %d\n",
1936 plane_wm, cursor_wm);
1937 enabled |= 1 << PIPE_B;
1941 * Calculate and update the self-refresh watermark only when one
1942 * display plane is used.
1944 * SNB support 3 levels of watermark.
1946 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1947 * and disabled in the descending order
1950 I915_WRITE(WM3_LP_ILK, 0);
1951 I915_WRITE(WM2_LP_ILK, 0);
1952 I915_WRITE(WM1_LP_ILK, 0);
1954 if (!single_plane_enabled(enabled) ||
1955 dev_priv->sprite_scaling_enabled)
1957 enabled = ffs(enabled) - 1;
1960 if (!ironlake_compute_srwm(dev, 1, enabled,
1961 dev_priv->wm.pri_latency[1] * 500,
1962 &sandybridge_display_srwm_info,
1963 &sandybridge_cursor_srwm_info,
1964 &fbc_wm, &plane_wm, &cursor_wm))
1967 I915_WRITE(WM1_LP_ILK,
1969 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1970 (fbc_wm << WM1_LP_FBC_SHIFT) |
1971 (plane_wm << WM1_LP_SR_SHIFT) |
1975 if (!ironlake_compute_srwm(dev, 2, enabled,
1976 dev_priv->wm.pri_latency[2] * 500,
1977 &sandybridge_display_srwm_info,
1978 &sandybridge_cursor_srwm_info,
1979 &fbc_wm, &plane_wm, &cursor_wm))
1982 I915_WRITE(WM2_LP_ILK,
1984 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1985 (fbc_wm << WM1_LP_FBC_SHIFT) |
1986 (plane_wm << WM1_LP_SR_SHIFT) |
1990 if (!ironlake_compute_srwm(dev, 3, enabled,
1991 dev_priv->wm.pri_latency[3] * 500,
1992 &sandybridge_display_srwm_info,
1993 &sandybridge_cursor_srwm_info,
1994 &fbc_wm, &plane_wm, &cursor_wm))
1997 I915_WRITE(WM3_LP_ILK,
1999 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2000 (fbc_wm << WM1_LP_FBC_SHIFT) |
2001 (plane_wm << WM1_LP_SR_SHIFT) |
2005 static void ivybridge_update_wm(struct drm_crtc *crtc)
2007 struct drm_device *dev = crtc->dev;
2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
2011 int fbc_wm, plane_wm, cursor_wm;
2012 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2013 unsigned int enabled;
2016 if (g4x_compute_wm0(dev, PIPE_A,
2017 &sandybridge_display_wm_info, latency,
2018 &sandybridge_cursor_wm_info, latency,
2019 &plane_wm, &cursor_wm)) {
2020 val = I915_READ(WM0_PIPEA_ILK);
2021 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2022 I915_WRITE(WM0_PIPEA_ILK, val |
2023 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2024 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2025 " plane %d, " "cursor: %d\n",
2026 plane_wm, cursor_wm);
2027 enabled |= 1 << PIPE_A;
2030 if (g4x_compute_wm0(dev, PIPE_B,
2031 &sandybridge_display_wm_info, latency,
2032 &sandybridge_cursor_wm_info, latency,
2033 &plane_wm, &cursor_wm)) {
2034 val = I915_READ(WM0_PIPEB_ILK);
2035 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2036 I915_WRITE(WM0_PIPEB_ILK, val |
2037 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2038 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2039 " plane %d, cursor: %d\n",
2040 plane_wm, cursor_wm);
2041 enabled |= 1 << PIPE_B;
2044 if (g4x_compute_wm0(dev, PIPE_C,
2045 &sandybridge_display_wm_info, latency,
2046 &sandybridge_cursor_wm_info, latency,
2047 &plane_wm, &cursor_wm)) {
2048 val = I915_READ(WM0_PIPEC_IVB);
2049 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2050 I915_WRITE(WM0_PIPEC_IVB, val |
2051 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2052 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2053 " plane %d, cursor: %d\n",
2054 plane_wm, cursor_wm);
2055 enabled |= 1 << PIPE_C;
2059 * Calculate and update the self-refresh watermark only when one
2060 * display plane is used.
2062 * SNB support 3 levels of watermark.
2064 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2065 * and disabled in the descending order
2068 I915_WRITE(WM3_LP_ILK, 0);
2069 I915_WRITE(WM2_LP_ILK, 0);
2070 I915_WRITE(WM1_LP_ILK, 0);
2072 if (!single_plane_enabled(enabled) ||
2073 dev_priv->sprite_scaling_enabled)
2075 enabled = ffs(enabled) - 1;
2078 if (!ironlake_compute_srwm(dev, 1, enabled,
2079 dev_priv->wm.pri_latency[1] * 500,
2080 &sandybridge_display_srwm_info,
2081 &sandybridge_cursor_srwm_info,
2082 &fbc_wm, &plane_wm, &cursor_wm))
2085 I915_WRITE(WM1_LP_ILK,
2087 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2088 (fbc_wm << WM1_LP_FBC_SHIFT) |
2089 (plane_wm << WM1_LP_SR_SHIFT) |
2093 if (!ironlake_compute_srwm(dev, 2, enabled,
2094 dev_priv->wm.pri_latency[2] * 500,
2095 &sandybridge_display_srwm_info,
2096 &sandybridge_cursor_srwm_info,
2097 &fbc_wm, &plane_wm, &cursor_wm))
2100 I915_WRITE(WM2_LP_ILK,
2102 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2103 (fbc_wm << WM1_LP_FBC_SHIFT) |
2104 (plane_wm << WM1_LP_SR_SHIFT) |
2107 /* WM3, note we have to correct the cursor latency */
2108 if (!ironlake_compute_srwm(dev, 3, enabled,
2109 dev_priv->wm.pri_latency[3] * 500,
2110 &sandybridge_display_srwm_info,
2111 &sandybridge_cursor_srwm_info,
2112 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2113 !ironlake_compute_srwm(dev, 3, enabled,
2114 dev_priv->wm.cur_latency[3] * 500,
2115 &sandybridge_display_srwm_info,
2116 &sandybridge_cursor_srwm_info,
2117 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2120 I915_WRITE(WM3_LP_ILK,
2122 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2123 (fbc_wm << WM1_LP_FBC_SHIFT) |
2124 (plane_wm << WM1_LP_SR_SHIFT) |
2128 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2129 struct drm_crtc *crtc)
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132 uint32_t pixel_rate;
2134 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2136 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2137 * adjust the pixel_rate here. */
2139 if (intel_crtc->config.pch_pfit.enabled) {
2140 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2141 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2143 pipe_w = intel_crtc->config.pipe_src_w;
2144 pipe_h = intel_crtc->config.pipe_src_h;
2145 pfit_w = (pfit_size >> 16) & 0xFFFF;
2146 pfit_h = pfit_size & 0xFFFF;
2147 if (pipe_w < pfit_w)
2149 if (pipe_h < pfit_h)
2152 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2159 /* latency must be in 0.1us units. */
2160 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2165 if (WARN(latency == 0, "Latency value missing\n"))
2168 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2169 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2174 /* latency must be in 0.1us units. */
2175 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2176 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2181 if (WARN(latency == 0, "Latency value missing\n"))
2184 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2185 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2186 ret = DIV_ROUND_UP(ret, 64) + 2;
2190 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2191 uint8_t bytes_per_pixel)
2193 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2196 struct hsw_pipe_wm_parameters {
2198 uint32_t pipe_htotal;
2199 uint32_t pixel_rate;
2200 struct intel_plane_wm_parameters pri;
2201 struct intel_plane_wm_parameters spr;
2202 struct intel_plane_wm_parameters cur;
2205 struct hsw_wm_maximums {
2212 /* used in computing the new watermarks state */
2213 struct intel_wm_config {
2214 unsigned int num_pipes_active;
2215 bool sprites_enabled;
2216 bool sprites_scaled;
2220 * For both WM_PIPE and WM_LP.
2221 * mem_value must be in 0.1us units.
2223 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2227 uint32_t method1, method2;
2229 if (!params->active || !params->pri.enabled)
2232 method1 = ilk_wm_method1(params->pixel_rate,
2233 params->pri.bytes_per_pixel,
2239 method2 = ilk_wm_method2(params->pixel_rate,
2240 params->pipe_htotal,
2241 params->pri.horiz_pixels,
2242 params->pri.bytes_per_pixel,
2245 return min(method1, method2);
2249 * For both WM_PIPE and WM_LP.
2250 * mem_value must be in 0.1us units.
2252 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2255 uint32_t method1, method2;
2257 if (!params->active || !params->spr.enabled)
2260 method1 = ilk_wm_method1(params->pixel_rate,
2261 params->spr.bytes_per_pixel,
2263 method2 = ilk_wm_method2(params->pixel_rate,
2264 params->pipe_htotal,
2265 params->spr.horiz_pixels,
2266 params->spr.bytes_per_pixel,
2268 return min(method1, method2);
2272 * For both WM_PIPE and WM_LP.
2273 * mem_value must be in 0.1us units.
2275 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2278 if (!params->active || !params->cur.enabled)
2281 return ilk_wm_method2(params->pixel_rate,
2282 params->pipe_htotal,
2283 params->cur.horiz_pixels,
2284 params->cur.bytes_per_pixel,
2288 /* Only for WM_LP. */
2289 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2292 if (!params->active || !params->pri.enabled)
2295 return ilk_wm_fbc(pri_val,
2296 params->pri.horiz_pixels,
2297 params->pri.bytes_per_pixel);
2300 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2302 if (INTEL_INFO(dev)->gen >= 8)
2304 else if (INTEL_INFO(dev)->gen >= 7)
2310 /* Calculate the maximum primary/sprite plane watermark */
2311 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2313 const struct intel_wm_config *config,
2314 enum intel_ddb_partitioning ddb_partitioning,
2317 unsigned int fifo_size = ilk_display_fifo_size(dev);
2320 /* if sprites aren't enabled, sprites get nothing */
2321 if (is_sprite && !config->sprites_enabled)
2324 /* HSW allows LP1+ watermarks even with multiple pipes */
2325 if (level == 0 || config->num_pipes_active > 1) {
2326 fifo_size /= INTEL_INFO(dev)->num_pipes;
2329 * For some reason the non self refresh
2330 * FIFO size is only half of the self
2331 * refresh FIFO size on ILK/SNB.
2333 if (INTEL_INFO(dev)->gen <= 6)
2337 if (config->sprites_enabled) {
2338 /* level 0 is always calculated with 1:1 split */
2339 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2348 /* clamp to max that the registers can hold */
2349 if (INTEL_INFO(dev)->gen >= 8)
2350 max = level == 0 ? 255 : 2047;
2351 else if (INTEL_INFO(dev)->gen >= 7)
2352 /* IVB/HSW primary/sprite plane watermarks */
2353 max = level == 0 ? 127 : 1023;
2354 else if (!is_sprite)
2355 /* ILK/SNB primary plane watermarks */
2356 max = level == 0 ? 127 : 511;
2358 /* ILK/SNB sprite plane watermarks */
2359 max = level == 0 ? 63 : 255;
2361 return min(fifo_size, max);
2364 /* Calculate the maximum cursor plane watermark */
2365 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2367 const struct intel_wm_config *config)
2369 /* HSW LP1+ watermarks w/ multiple pipes */
2370 if (level > 0 && config->num_pipes_active > 1)
2373 /* otherwise just report max that registers can hold */
2374 if (INTEL_INFO(dev)->gen >= 7)
2375 return level == 0 ? 63 : 255;
2377 return level == 0 ? 31 : 63;
2380 /* Calculate the maximum FBC watermark */
2381 static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
2383 /* max that registers can hold */
2384 if (INTEL_INFO(dev)->gen >= 8)
2390 static void ilk_compute_wm_maximums(struct drm_device *dev,
2392 const struct intel_wm_config *config,
2393 enum intel_ddb_partitioning ddb_partitioning,
2394 struct hsw_wm_maximums *max)
2396 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2397 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2398 max->cur = ilk_cursor_wm_max(dev, level, config);
2399 max->fbc = ilk_fbc_wm_max(dev);
2402 static bool ilk_validate_wm_level(int level,
2403 const struct hsw_wm_maximums *max,
2404 struct intel_wm_level *result)
2408 /* already determined to be invalid? */
2409 if (!result->enable)
2412 result->enable = result->pri_val <= max->pri &&
2413 result->spr_val <= max->spr &&
2414 result->cur_val <= max->cur;
2416 ret = result->enable;
2419 * HACK until we can pre-compute everything,
2420 * and thus fail gracefully if LP0 watermarks
2423 if (level == 0 && !result->enable) {
2424 if (result->pri_val > max->pri)
2425 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2426 level, result->pri_val, max->pri);
2427 if (result->spr_val > max->spr)
2428 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2429 level, result->spr_val, max->spr);
2430 if (result->cur_val > max->cur)
2431 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2432 level, result->cur_val, max->cur);
2434 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2435 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2436 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2437 result->enable = true;
2443 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2445 const struct hsw_pipe_wm_parameters *p,
2446 struct intel_wm_level *result)
2448 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2449 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2450 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2452 /* WM1+ latency values stored in 0.5us units */
2459 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2460 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2461 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2462 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2463 result->enable = true;
2467 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2471 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2472 u32 linetime, ips_linetime;
2474 if (!intel_crtc_active(crtc))
2477 /* The WM are computed with base on how long it takes to fill a single
2478 * row at the given clock rate, multiplied by 8.
2480 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2482 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2483 intel_ddi_get_cdclk_freq(dev_priv));
2485 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2486 PIPE_WM_LINETIME_TIME(linetime);
2489 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2493 if (IS_HASWELL(dev)) {
2494 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2496 wm[0] = (sskpd >> 56) & 0xFF;
2498 wm[0] = sskpd & 0xF;
2499 wm[1] = (sskpd >> 4) & 0xFF;
2500 wm[2] = (sskpd >> 12) & 0xFF;
2501 wm[3] = (sskpd >> 20) & 0x1FF;
2502 wm[4] = (sskpd >> 32) & 0x1FF;
2503 } else if (INTEL_INFO(dev)->gen >= 6) {
2504 uint32_t sskpd = I915_READ(MCH_SSKPD);
2506 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2507 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2508 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2509 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2510 } else if (INTEL_INFO(dev)->gen >= 5) {
2511 uint32_t mltr = I915_READ(MLTR_ILK);
2513 /* ILK primary LP0 latency is 700 ns */
2515 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2516 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2520 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2522 /* ILK sprite LP0 latency is 1300 ns */
2523 if (INTEL_INFO(dev)->gen == 5)
2527 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2529 /* ILK cursor LP0 latency is 1300 ns */
2530 if (INTEL_INFO(dev)->gen == 5)
2533 /* WaDoubleCursorLP3Latency:ivb */
2534 if (IS_IVYBRIDGE(dev))
2538 static int ilk_wm_max_level(const struct drm_device *dev)
2540 /* how many WM levels are we expecting */
2541 if (IS_HASWELL(dev))
2543 else if (INTEL_INFO(dev)->gen >= 6)
2549 static void intel_print_wm_latency(struct drm_device *dev,
2551 const uint16_t wm[5])
2553 int level, max_level = ilk_wm_max_level(dev);
2555 for (level = 0; level <= max_level; level++) {
2556 unsigned int latency = wm[level];
2559 DRM_ERROR("%s WM%d latency not provided\n",
2564 /* WM1+ latency values in 0.5us units */
2568 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2569 name, level, wm[level],
2570 latency / 10, latency % 10);
2574 static void intel_setup_wm_latency(struct drm_device *dev)
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2578 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2580 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2581 sizeof(dev_priv->wm.pri_latency));
2582 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2583 sizeof(dev_priv->wm.pri_latency));
2585 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2586 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2588 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2589 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2590 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2593 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2594 struct hsw_pipe_wm_parameters *p,
2595 struct intel_wm_config *config)
2597 struct drm_device *dev = crtc->dev;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 enum pipe pipe = intel_crtc->pipe;
2600 struct drm_plane *plane;
2602 p->active = intel_crtc_active(crtc);
2604 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2605 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2606 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2607 p->cur.bytes_per_pixel = 4;
2608 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2609 p->cur.horiz_pixels = 64;
2610 /* TODO: for now, assume primary and cursor planes are always enabled. */
2611 p->pri.enabled = true;
2612 p->cur.enabled = true;
2615 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2616 config->num_pipes_active += intel_crtc_active(crtc);
2618 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2619 struct intel_plane *intel_plane = to_intel_plane(plane);
2621 if (intel_plane->pipe == pipe)
2622 p->spr = intel_plane->wm;
2624 config->sprites_enabled |= intel_plane->wm.enabled;
2625 config->sprites_scaled |= intel_plane->wm.scaled;
2629 /* Compute new watermarks for the pipe */
2630 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2631 const struct hsw_pipe_wm_parameters *params,
2632 struct intel_pipe_wm *pipe_wm)
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 int level, max_level = ilk_wm_max_level(dev);
2637 /* LP0 watermark maximums depend on this pipe alone */
2638 struct intel_wm_config config = {
2639 .num_pipes_active = 1,
2640 .sprites_enabled = params->spr.enabled,
2641 .sprites_scaled = params->spr.scaled,
2643 struct hsw_wm_maximums max;
2645 /* LP0 watermarks always use 1/2 DDB partitioning */
2646 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2648 for (level = 0; level <= max_level; level++)
2649 ilk_compute_wm_level(dev_priv, level, params,
2650 &pipe_wm->wm[level]);
2652 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2654 /* At least LP0 must be valid */
2655 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2659 * Merge the watermarks from all active pipes for a specific level.
2661 static void ilk_merge_wm_level(struct drm_device *dev,
2663 struct intel_wm_level *ret_wm)
2665 const struct intel_crtc *intel_crtc;
2667 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2668 const struct intel_wm_level *wm =
2669 &intel_crtc->wm.active.wm[level];
2674 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2675 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2676 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2677 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2680 ret_wm->enable = true;
2684 * Merge all low power watermarks for all active pipes.
2686 static void ilk_wm_merge(struct drm_device *dev,
2687 const struct hsw_wm_maximums *max,
2688 struct intel_pipe_wm *merged)
2690 int level, max_level = ilk_wm_max_level(dev);
2692 merged->fbc_wm_enabled = true;
2694 /* merge each WM1+ level */
2695 for (level = 1; level <= max_level; level++) {
2696 struct intel_wm_level *wm = &merged->wm[level];
2698 ilk_merge_wm_level(dev, level, wm);
2700 if (!ilk_validate_wm_level(level, max, wm))
2704 * The spec says it is preferred to disable
2705 * FBC WMs instead of disabling a WM level.
2707 if (wm->fbc_val > max->fbc) {
2708 merged->fbc_wm_enabled = false;
2714 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2716 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2717 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2720 static void hsw_compute_wm_results(struct drm_device *dev,
2721 const struct intel_pipe_wm *merged,
2722 enum intel_ddb_partitioning partitioning,
2723 struct hsw_wm_values *results)
2725 struct intel_crtc *intel_crtc;
2728 results->enable_fbc_wm = merged->fbc_wm_enabled;
2729 results->partitioning = partitioning;
2731 /* LP1+ register values */
2732 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2733 const struct intel_wm_level *r;
2735 level = ilk_wm_lp_to_level(wm_lp, merged);
2737 r = &merged->wm[level];
2741 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2742 ((level * 2) << WM1_LP_LATENCY_SHIFT) |
2743 (r->pri_val << WM1_LP_SR_SHIFT) |
2746 if (INTEL_INFO(dev)->gen >= 8)
2747 results->wm_lp[wm_lp - 1] |=
2748 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2750 results->wm_lp[wm_lp - 1] |=
2751 r->fbc_val << WM1_LP_FBC_SHIFT;
2753 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2756 /* LP0 register values */
2757 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2758 enum pipe pipe = intel_crtc->pipe;
2759 const struct intel_wm_level *r =
2760 &intel_crtc->wm.active.wm[0];
2762 if (WARN_ON(!r->enable))
2765 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2767 results->wm_pipe[pipe] =
2768 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2769 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2774 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2775 * case both are at the same level. Prefer r1 in case they're the same. */
2776 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2777 struct intel_pipe_wm *r1,
2778 struct intel_pipe_wm *r2)
2780 int level, max_level = ilk_wm_max_level(dev);
2781 int level1 = 0, level2 = 0;
2783 for (level = 1; level <= max_level; level++) {
2784 if (r1->wm[level].enable)
2786 if (r2->wm[level].enable)
2790 if (level1 == level2) {
2791 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2795 } else if (level1 > level2) {
2802 /* dirty bits used to track which watermarks need changes */
2803 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2804 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2805 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2806 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2807 #define WM_DIRTY_FBC (1 << 24)
2808 #define WM_DIRTY_DDB (1 << 25)
2810 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2811 const struct hsw_wm_values *old,
2812 const struct hsw_wm_values *new)
2814 unsigned int dirty = 0;
2818 for_each_pipe(pipe) {
2819 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2820 dirty |= WM_DIRTY_LINETIME(pipe);
2821 /* Must disable LP1+ watermarks too */
2822 dirty |= WM_DIRTY_LP_ALL;
2825 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2826 dirty |= WM_DIRTY_PIPE(pipe);
2827 /* Must disable LP1+ watermarks too */
2828 dirty |= WM_DIRTY_LP_ALL;
2832 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2833 dirty |= WM_DIRTY_FBC;
2834 /* Must disable LP1+ watermarks too */
2835 dirty |= WM_DIRTY_LP_ALL;
2838 if (old->partitioning != new->partitioning) {
2839 dirty |= WM_DIRTY_DDB;
2840 /* Must disable LP1+ watermarks too */
2841 dirty |= WM_DIRTY_LP_ALL;
2844 /* LP1+ watermarks already deemed dirty, no need to continue */
2845 if (dirty & WM_DIRTY_LP_ALL)
2848 /* Find the lowest numbered LP1+ watermark in need of an update... */
2849 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2850 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2851 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2855 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2856 for (; wm_lp <= 3; wm_lp++)
2857 dirty |= WM_DIRTY_LP(wm_lp);
2863 * The spec says we shouldn't write when we don't need, because every write
2864 * causes WMs to be re-evaluated, expending some power.
2866 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2867 struct hsw_wm_values *results)
2869 struct hsw_wm_values *previous = &dev_priv->wm.hw;
2873 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2877 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2878 I915_WRITE(WM3_LP_ILK, 0);
2879 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2880 I915_WRITE(WM2_LP_ILK, 0);
2881 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2882 I915_WRITE(WM1_LP_ILK, 0);
2884 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2885 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2886 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2887 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2888 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2889 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2891 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2892 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2893 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2894 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2895 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2896 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2898 if (dirty & WM_DIRTY_DDB) {
2899 val = I915_READ(WM_MISC);
2900 if (results->partitioning == INTEL_DDB_PART_1_2)
2901 val &= ~WM_MISC_DATA_PARTITION_5_6;
2903 val |= WM_MISC_DATA_PARTITION_5_6;
2904 I915_WRITE(WM_MISC, val);
2907 if (dirty & WM_DIRTY_FBC) {
2908 val = I915_READ(DISP_ARB_CTL);
2909 if (results->enable_fbc_wm)
2910 val &= ~DISP_FBC_WM_DIS;
2912 val |= DISP_FBC_WM_DIS;
2913 I915_WRITE(DISP_ARB_CTL, val);
2916 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2917 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2918 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2919 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2920 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2921 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2923 if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2924 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2925 if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2926 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2927 if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2928 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2930 dev_priv->wm.hw = *results;
2933 static void haswell_update_wm(struct drm_crtc *crtc)
2935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936 struct drm_device *dev = crtc->dev;
2937 struct drm_i915_private *dev_priv = dev->dev_private;
2938 struct hsw_wm_maximums max;
2939 struct hsw_pipe_wm_parameters params = {};
2940 struct hsw_wm_values results = {};
2941 enum intel_ddb_partitioning partitioning;
2942 struct intel_pipe_wm pipe_wm = {};
2943 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2944 struct intel_wm_config config = {};
2946 hsw_compute_wm_parameters(crtc, ¶ms, &config);
2948 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
2950 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2953 intel_crtc->wm.active = pipe_wm;
2955 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2956 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2958 /* 5/6 split only in single pipe config on IVB+ */
2959 if (INTEL_INFO(dev)->gen >= 7 &&
2960 config.num_pipes_active == 1 && config.sprites_enabled) {
2961 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2962 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2964 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2966 best_lp_wm = &lp_wm_1_2;
2969 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2970 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2972 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2974 hsw_write_wm_values(dev_priv, &results);
2977 static void haswell_update_sprite_wm(struct drm_plane *plane,
2978 struct drm_crtc *crtc,
2979 uint32_t sprite_width, int pixel_size,
2980 bool enabled, bool scaled)
2982 struct intel_plane *intel_plane = to_intel_plane(plane);
2984 intel_plane->wm.enabled = enabled;
2985 intel_plane->wm.scaled = scaled;
2986 intel_plane->wm.horiz_pixels = sprite_width;
2987 intel_plane->wm.bytes_per_pixel = pixel_size;
2989 haswell_update_wm(crtc);
2993 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2994 uint32_t sprite_width, int pixel_size,
2995 const struct intel_watermark_params *display,
2996 int display_latency_ns, int *sprite_wm)
2998 struct drm_crtc *crtc;
3000 int entries, tlb_miss;
3002 crtc = intel_get_crtc_for_plane(dev, plane);
3003 if (!intel_crtc_active(crtc)) {
3004 *sprite_wm = display->guard_size;
3008 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3010 /* Use the small buffer method to calculate the sprite watermark */
3011 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3012 tlb_miss = display->fifo_size*display->cacheline_size -
3015 entries += tlb_miss;
3016 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3017 *sprite_wm = entries + display->guard_size;
3018 if (*sprite_wm > (int)display->max_wm)
3019 *sprite_wm = display->max_wm;
3025 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3026 uint32_t sprite_width, int pixel_size,
3027 const struct intel_watermark_params *display,
3028 int latency_ns, int *sprite_wm)
3030 struct drm_crtc *crtc;
3031 unsigned long line_time_us;
3033 int line_count, line_size;
3042 crtc = intel_get_crtc_for_plane(dev, plane);
3043 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3049 line_time_us = (sprite_width * 1000) / clock;
3050 if (!line_time_us) {
3055 line_count = (latency_ns / line_time_us + 1000) / 1000;
3056 line_size = sprite_width * pixel_size;
3058 /* Use the minimum of the small and large buffer method for primary */
3059 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3060 large = line_count * line_size;
3062 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3063 *sprite_wm = entries + display->guard_size;
3065 return *sprite_wm > 0x3ff ? false : true;
3068 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3069 struct drm_crtc *crtc,
3070 uint32_t sprite_width, int pixel_size,
3071 bool enabled, bool scaled)
3073 struct drm_device *dev = plane->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 int pipe = to_intel_plane(plane)->pipe;
3076 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
3086 reg = WM0_PIPEA_ILK;
3089 reg = WM0_PIPEB_ILK;
3092 reg = WM0_PIPEC_IVB;
3095 return; /* bad pipe */
3098 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3099 &sandybridge_display_wm_info,
3100 latency, &sprite_wm);
3102 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3107 val = I915_READ(reg);
3108 val &= ~WM0_PIPE_SPRITE_MASK;
3109 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3110 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3113 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3115 &sandybridge_display_srwm_info,
3116 dev_priv->wm.spr_latency[1] * 500,
3119 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3123 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3125 /* Only IVB has two more LP watermarks for sprite */
3126 if (!IS_IVYBRIDGE(dev))
3129 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3131 &sandybridge_display_srwm_info,
3132 dev_priv->wm.spr_latency[2] * 500,
3135 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3139 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3141 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3143 &sandybridge_display_srwm_info,
3144 dev_priv->wm.spr_latency[3] * 500,
3147 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3151 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3154 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3156 struct drm_device *dev = crtc->dev;
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3160 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3161 enum pipe pipe = intel_crtc->pipe;
3162 static const unsigned int wm0_pipe_reg[] = {
3163 [PIPE_A] = WM0_PIPEA_ILK,
3164 [PIPE_B] = WM0_PIPEB_ILK,
3165 [PIPE_C] = WM0_PIPEC_IVB,
3168 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3169 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3171 if (intel_crtc_active(crtc)) {
3172 u32 tmp = hw->wm_pipe[pipe];
3175 * For active pipes LP0 watermark is marked as
3176 * enabled, and LP1+ watermaks as disabled since
3177 * we can't really reverse compute them in case
3178 * multiple pipes are active.
3180 active->wm[0].enable = true;
3181 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3182 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3183 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3184 active->linetime = hw->wm_linetime[pipe];
3186 int level, max_level = ilk_wm_max_level(dev);
3189 * For inactive pipes, all watermark levels
3190 * should be marked as enabled but zeroed,
3191 * which is what we'd compute them to.
3193 for (level = 0; level <= max_level; level++)
3194 active->wm[level].enable = true;
3198 void ilk_wm_get_hw_state(struct drm_device *dev)
3200 struct drm_i915_private *dev_priv = dev->dev_private;
3201 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3202 struct drm_crtc *crtc;
3204 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3205 ilk_pipe_wm_get_hw_state(crtc);
3207 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3208 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3209 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3211 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3212 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3213 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3215 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3216 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3219 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3223 * intel_update_watermarks - update FIFO watermark values based on current modes
3225 * Calculate watermark values for the various WM regs based on current mode
3226 * and plane configuration.
3228 * There are several cases to deal with here:
3229 * - normal (i.e. non-self-refresh)
3230 * - self-refresh (SR) mode
3231 * - lines are large relative to FIFO size (buffer can hold up to 2)
3232 * - lines are small relative to FIFO size (buffer can hold more than 2
3233 * lines), so need to account for TLB latency
3235 * The normal calculation is:
3236 * watermark = dotclock * bytes per pixel * latency
3237 * where latency is platform & configuration dependent (we assume pessimal
3240 * The SR calculation is:
3241 * watermark = (trunc(latency/line time)+1) * surface width *
3244 * line time = htotal / dotclock
3245 * surface width = hdisplay for normal plane and 64 for cursor
3246 * and latency is assumed to be high, as above.
3248 * The final value programmed to the register should always be rounded up,
3249 * and include an extra 2 entries to account for clock crossings.
3251 * We don't use the sprite, so we can ignore that. And on Crestline we have
3252 * to set the non-SR watermarks to 8.
3254 void intel_update_watermarks(struct drm_crtc *crtc)
3256 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3258 if (dev_priv->display.update_wm)
3259 dev_priv->display.update_wm(crtc);
3262 void intel_update_sprite_watermarks(struct drm_plane *plane,
3263 struct drm_crtc *crtc,
3264 uint32_t sprite_width, int pixel_size,
3265 bool enabled, bool scaled)
3267 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3269 if (dev_priv->display.update_sprite_wm)
3270 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3271 pixel_size, enabled, scaled);
3274 static struct drm_i915_gem_object *
3275 intel_alloc_context_page(struct drm_device *dev)
3277 struct drm_i915_gem_object *ctx;
3280 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3282 ctx = i915_gem_alloc_object(dev, 4096);
3284 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3288 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3290 DRM_ERROR("failed to pin power context: %d\n", ret);
3294 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3296 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3303 i915_gem_object_unpin(ctx);
3305 drm_gem_object_unreference(&ctx->base);
3310 * Lock protecting IPS related data structures
3312 DEFINE_SPINLOCK(mchdev_lock);
3314 /* Global for IPS driver to get at the current i915 device. Protected by
3316 static struct drm_i915_private *i915_mch_dev;
3318 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3323 assert_spin_locked(&mchdev_lock);
3325 rgvswctl = I915_READ16(MEMSWCTL);
3326 if (rgvswctl & MEMCTL_CMD_STS) {
3327 DRM_DEBUG("gpu busy, RCS change rejected\n");
3328 return false; /* still busy with another command */
3331 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3332 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3333 I915_WRITE16(MEMSWCTL, rgvswctl);
3334 POSTING_READ16(MEMSWCTL);
3336 rgvswctl |= MEMCTL_CMD_STS;
3337 I915_WRITE16(MEMSWCTL, rgvswctl);
3342 static void ironlake_enable_drps(struct drm_device *dev)
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 u32 rgvmodectl = I915_READ(MEMMODECTL);
3346 u8 fmax, fmin, fstart, vstart;
3348 spin_lock_irq(&mchdev_lock);
3350 /* Enable temp reporting */
3351 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3352 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3354 /* 100ms RC evaluation intervals */
3355 I915_WRITE(RCUPEI, 100000);
3356 I915_WRITE(RCDNEI, 100000);
3358 /* Set max/min thresholds to 90ms and 80ms respectively */
3359 I915_WRITE(RCBMAXAVG, 90000);
3360 I915_WRITE(RCBMINAVG, 80000);
3362 I915_WRITE(MEMIHYST, 1);
3364 /* Set up min, max, and cur for interrupt handling */
3365 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3366 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3367 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3368 MEMMODE_FSTART_SHIFT;
3370 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3373 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3374 dev_priv->ips.fstart = fstart;
3376 dev_priv->ips.max_delay = fstart;
3377 dev_priv->ips.min_delay = fmin;
3378 dev_priv->ips.cur_delay = fstart;
3380 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3381 fmax, fmin, fstart);
3383 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3386 * Interrupts will be enabled in ironlake_irq_postinstall
3389 I915_WRITE(VIDSTART, vstart);
3390 POSTING_READ(VIDSTART);
3392 rgvmodectl |= MEMMODE_SWMODE_EN;
3393 I915_WRITE(MEMMODECTL, rgvmodectl);
3395 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3396 DRM_ERROR("stuck trying to change perf mode\n");
3399 ironlake_set_drps(dev, fstart);
3401 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3403 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3404 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3405 getrawmonotonic(&dev_priv->ips.last_time2);
3407 spin_unlock_irq(&mchdev_lock);
3410 static void ironlake_disable_drps(struct drm_device *dev)
3412 struct drm_i915_private *dev_priv = dev->dev_private;
3415 spin_lock_irq(&mchdev_lock);
3417 rgvswctl = I915_READ16(MEMSWCTL);
3419 /* Ack interrupts, disable EFC interrupt */
3420 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3421 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3422 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3423 I915_WRITE(DEIIR, DE_PCU_EVENT);
3424 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3426 /* Go back to the starting frequency */
3427 ironlake_set_drps(dev, dev_priv->ips.fstart);
3429 rgvswctl |= MEMCTL_CMD_STS;
3430 I915_WRITE(MEMSWCTL, rgvswctl);
3433 spin_unlock_irq(&mchdev_lock);
3436 /* There's a funny hw issue where the hw returns all 0 when reading from
3437 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3438 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3439 * all limits and the gpu stuck at whatever frequency it is at atm).
3441 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3445 /* Only set the down limit when we've reached the lowest level to avoid
3446 * getting more interrupts, otherwise leave this clear. This prevents a
3447 * race in the hw when coming out of rc6: There's a tiny window where
3448 * the hw runs at the minimal clock before selecting the desired
3449 * frequency, if the down threshold expires in that window we will not
3450 * receive a down interrupt. */
3451 limits = dev_priv->rps.max_delay << 24;
3452 if (val <= dev_priv->rps.min_delay)
3453 limits |= dev_priv->rps.min_delay << 16;
3458 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3462 new_power = dev_priv->rps.power;
3463 switch (dev_priv->rps.power) {
3465 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3466 new_power = BETWEEN;
3470 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3471 new_power = LOW_POWER;
3472 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3473 new_power = HIGH_POWER;
3477 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3478 new_power = BETWEEN;
3481 /* Max/min bins are special */
3482 if (val == dev_priv->rps.min_delay)
3483 new_power = LOW_POWER;
3484 if (val == dev_priv->rps.max_delay)
3485 new_power = HIGH_POWER;
3486 if (new_power == dev_priv->rps.power)
3489 /* Note the units here are not exactly 1us, but 1280ns. */
3490 switch (new_power) {
3492 /* Upclock if more than 95% busy over 16ms */
3493 I915_WRITE(GEN6_RP_UP_EI, 12500);
3494 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3496 /* Downclock if less than 85% busy over 32ms */
3497 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3498 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3500 I915_WRITE(GEN6_RP_CONTROL,
3501 GEN6_RP_MEDIA_TURBO |
3502 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3503 GEN6_RP_MEDIA_IS_GFX |
3505 GEN6_RP_UP_BUSY_AVG |
3506 GEN6_RP_DOWN_IDLE_AVG);
3510 /* Upclock if more than 90% busy over 13ms */
3511 I915_WRITE(GEN6_RP_UP_EI, 10250);
3512 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3514 /* Downclock if less than 75% busy over 32ms */
3515 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3516 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3518 I915_WRITE(GEN6_RP_CONTROL,
3519 GEN6_RP_MEDIA_TURBO |
3520 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3521 GEN6_RP_MEDIA_IS_GFX |
3523 GEN6_RP_UP_BUSY_AVG |
3524 GEN6_RP_DOWN_IDLE_AVG);
3528 /* Upclock if more than 85% busy over 10ms */
3529 I915_WRITE(GEN6_RP_UP_EI, 8000);
3530 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3532 /* Downclock if less than 60% busy over 32ms */
3533 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3534 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3536 I915_WRITE(GEN6_RP_CONTROL,
3537 GEN6_RP_MEDIA_TURBO |
3538 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3539 GEN6_RP_MEDIA_IS_GFX |
3541 GEN6_RP_UP_BUSY_AVG |
3542 GEN6_RP_DOWN_IDLE_AVG);
3546 dev_priv->rps.power = new_power;
3547 dev_priv->rps.last_adj = 0;
3550 void gen6_set_rps(struct drm_device *dev, u8 val)
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3554 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3555 WARN_ON(val > dev_priv->rps.max_delay);
3556 WARN_ON(val < dev_priv->rps.min_delay);
3558 if (val == dev_priv->rps.cur_delay)
3561 gen6_set_rps_thresholds(dev_priv, val);
3563 if (IS_HASWELL(dev))
3564 I915_WRITE(GEN6_RPNSWREQ,
3565 HSW_FREQUENCY(val));
3567 I915_WRITE(GEN6_RPNSWREQ,
3568 GEN6_FREQUENCY(val) |
3570 GEN6_AGGRESSIVE_TURBO);
3572 /* Make sure we continue to get interrupts
3573 * until we hit the minimum or maximum frequencies.
3575 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3576 gen6_rps_limits(dev_priv, val));
3578 POSTING_READ(GEN6_RPNSWREQ);
3580 dev_priv->rps.cur_delay = val;
3582 trace_intel_gpu_freq_change(val * 50);
3585 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3587 mutex_lock(&dev_priv->rps.hw_lock);
3588 if (dev_priv->rps.enabled) {
3589 if (dev_priv->info->is_valleyview)
3590 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3592 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3593 dev_priv->rps.last_adj = 0;
3595 mutex_unlock(&dev_priv->rps.hw_lock);
3598 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3600 mutex_lock(&dev_priv->rps.hw_lock);
3601 if (dev_priv->rps.enabled) {
3602 if (dev_priv->info->is_valleyview)
3603 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3605 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3606 dev_priv->rps.last_adj = 0;
3608 mutex_unlock(&dev_priv->rps.hw_lock);
3611 void valleyview_set_rps(struct drm_device *dev, u8 val)
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3615 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3616 WARN_ON(val > dev_priv->rps.max_delay);
3617 WARN_ON(val < dev_priv->rps.min_delay);
3619 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3620 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3621 dev_priv->rps.cur_delay,
3622 vlv_gpu_freq(dev_priv, val), val);
3624 if (val == dev_priv->rps.cur_delay)
3627 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3629 dev_priv->rps.cur_delay = val;
3631 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3634 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3638 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3639 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3640 /* Complete PM interrupt masking here doesn't race with the rps work
3641 * item again unmasking PM interrupts because that is using a different
3642 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3643 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3645 spin_lock_irq(&dev_priv->irq_lock);
3646 dev_priv->rps.pm_iir = 0;
3647 spin_unlock_irq(&dev_priv->irq_lock);
3649 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3652 static void gen6_disable_rps(struct drm_device *dev)
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3656 I915_WRITE(GEN6_RC_CONTROL, 0);
3657 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3659 gen6_disable_rps_interrupts(dev);
3662 static void valleyview_disable_rps(struct drm_device *dev)
3664 struct drm_i915_private *dev_priv = dev->dev_private;
3666 I915_WRITE(GEN6_RC_CONTROL, 0);
3668 gen6_disable_rps_interrupts(dev);
3670 if (dev_priv->vlv_pctx) {
3671 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3672 dev_priv->vlv_pctx = NULL;
3676 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3679 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3681 if (IS_HASWELL(dev))
3682 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3684 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3685 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3686 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3687 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3690 int intel_enable_rc6(const struct drm_device *dev)
3692 /* No RC6 before Ironlake */
3693 if (INTEL_INFO(dev)->gen < 5)
3696 /* Respect the kernel parameter if it is set */
3697 if (i915_enable_rc6 >= 0)
3698 return i915_enable_rc6;
3700 /* Disable RC6 on Ironlake */
3701 if (INTEL_INFO(dev)->gen == 5)
3704 if (IS_HASWELL(dev))
3705 return INTEL_RC6_ENABLE;
3707 /* snb/ivb have more than one rc6 state. */
3708 if (INTEL_INFO(dev)->gen == 6)
3709 return INTEL_RC6_ENABLE;
3711 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3714 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3719 spin_lock_irq(&dev_priv->irq_lock);
3720 WARN_ON(dev_priv->rps.pm_iir);
3721 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3722 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3723 spin_unlock_irq(&dev_priv->irq_lock);
3725 /* only unmask PM interrupts we need. Mask all others. */
3726 enabled_intrs = GEN6_PM_RPS_EVENTS;
3728 /* IVB and SNB hard hangs on looping batchbuffer
3729 * if GEN6_PM_UP_EI_EXPIRED is masked.
3731 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3732 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3734 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3737 static void gen8_enable_rps(struct drm_device *dev)
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_ring_buffer *ring;
3741 uint32_t rc6_mask = 0, rp_state_cap;
3744 /* 1a: Software RC state - RC0 */
3745 I915_WRITE(GEN6_RC_STATE, 0);
3747 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3748 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3749 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3751 /* 2a: Disable RC states. */
3752 I915_WRITE(GEN6_RC_CONTROL, 0);
3754 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3756 /* 2b: Program RC6 thresholds.*/
3757 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3758 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3759 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3760 for_each_ring(ring, dev_priv, unused)
3761 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3762 I915_WRITE(GEN6_RC_SLEEP, 0);
3763 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3766 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3767 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3768 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3769 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3770 GEN6_RC_CTL_EI_MODE(1) |
3773 /* 4 Program defaults and thresholds for RPS*/
3774 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3775 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3776 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3777 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3779 /* Docs recommend 900MHz, and 300 MHz respectively */
3780 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3781 dev_priv->rps.max_delay << 24 |
3782 dev_priv->rps.min_delay << 16);
3784 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3785 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3786 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3787 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3789 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3792 I915_WRITE(GEN6_RP_CONTROL,
3793 GEN6_RP_MEDIA_TURBO |
3794 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3795 GEN6_RP_MEDIA_IS_GFX |
3797 GEN6_RP_UP_BUSY_AVG |
3798 GEN6_RP_DOWN_IDLE_AVG);
3800 /* 6: Ring frequency + overclocking (our driver does this later */
3802 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3804 gen6_enable_rps_interrupts(dev);
3806 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3809 static void gen6_enable_rps(struct drm_device *dev)
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_ring_buffer *ring;
3815 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3820 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3822 /* Here begins a magic sequence of register writes to enable
3823 * auto-downclocking.
3825 * Perhaps there might be some value in exposing these to
3828 I915_WRITE(GEN6_RC_STATE, 0);
3830 /* Clear the DBG now so we don't confuse earlier errors */
3831 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3832 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3833 I915_WRITE(GTFIFODBG, gtfifodbg);
3836 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3838 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3839 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3841 /* In units of 50MHz */
3842 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3843 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3844 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3845 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3846 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3847 dev_priv->rps.cur_delay = 0;
3849 /* disable the counters and set deterministic thresholds */
3850 I915_WRITE(GEN6_RC_CONTROL, 0);
3852 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3853 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3854 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3855 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3856 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3858 for_each_ring(ring, dev_priv, i)
3859 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3861 I915_WRITE(GEN6_RC_SLEEP, 0);
3862 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3863 if (IS_IVYBRIDGE(dev))
3864 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3866 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3867 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3868 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3870 /* Check if we are enabling RC6 */
3871 rc6_mode = intel_enable_rc6(dev_priv->dev);
3872 if (rc6_mode & INTEL_RC6_ENABLE)
3873 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3875 /* We don't use those on Haswell */
3876 if (!IS_HASWELL(dev)) {
3877 if (rc6_mode & INTEL_RC6p_ENABLE)
3878 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3880 if (rc6_mode & INTEL_RC6pp_ENABLE)
3881 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3884 intel_print_rc6_info(dev, rc6_mask);
3886 I915_WRITE(GEN6_RC_CONTROL,
3888 GEN6_RC_CTL_EI_MODE(1) |
3889 GEN6_RC_CTL_HW_ENABLE);
3891 /* Power down if completely idle for over 50ms */
3892 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3893 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3895 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3898 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3899 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3900 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3901 (dev_priv->rps.max_delay & 0xff) * 50,
3902 (pcu_mbox & 0xff) * 50);
3903 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3906 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3909 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3910 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3912 gen6_enable_rps_interrupts(dev);
3915 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3916 if (IS_GEN6(dev) && ret) {
3917 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3918 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3919 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3920 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3921 rc6vids &= 0xffff00;
3922 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3923 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3925 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3928 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3931 void gen6_update_ring_freq(struct drm_device *dev)
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3935 unsigned int gpu_freq;
3936 unsigned int max_ia_freq, min_ring_freq;
3937 int scaling_factor = 180;
3938 struct cpufreq_policy *policy;
3940 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3942 policy = cpufreq_cpu_get(0);
3944 max_ia_freq = policy->cpuinfo.max_freq;
3945 cpufreq_cpu_put(policy);
3948 * Default to measured freq if none found, PCU will ensure we
3951 max_ia_freq = tsc_khz;
3954 /* Convert from kHz to MHz */
3955 max_ia_freq /= 1000;
3957 min_ring_freq = I915_READ(DCLK) & 0xf;
3958 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3959 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3962 * For each potential GPU frequency, load a ring frequency we'd like
3963 * to use for memory access. We do this by specifying the IA frequency
3964 * the PCU should use as a reference to determine the ring frequency.
3966 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3968 int diff = dev_priv->rps.max_delay - gpu_freq;
3969 unsigned int ia_freq = 0, ring_freq = 0;
3971 if (INTEL_INFO(dev)->gen >= 8) {
3972 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3973 ring_freq = max(min_ring_freq, gpu_freq);
3974 } else if (IS_HASWELL(dev)) {
3975 ring_freq = mult_frac(gpu_freq, 5, 4);
3976 ring_freq = max(min_ring_freq, ring_freq);
3977 /* leave ia_freq as the default, chosen by cpufreq */
3979 /* On older processors, there is no separate ring
3980 * clock domain, so in order to boost the bandwidth
3981 * of the ring, we need to upclock the CPU (ia_freq).
3983 * For GPU frequencies less than 750MHz,
3984 * just use the lowest ring freq.
3986 if (gpu_freq < min_freq)
3989 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3990 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3993 sandybridge_pcode_write(dev_priv,
3994 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3995 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3996 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4001 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4005 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4007 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4009 rp0 = min_t(u32, rp0, 0xea);
4014 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4018 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4019 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4020 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4021 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4026 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4028 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4031 static void valleyview_setup_pctx(struct drm_device *dev)
4033 struct drm_i915_private *dev_priv = dev->dev_private;
4034 struct drm_i915_gem_object *pctx;
4035 unsigned long pctx_paddr;
4037 int pctx_size = 24*1024;
4039 pcbr = I915_READ(VLV_PCBR);
4041 /* BIOS set it up already, grab the pre-alloc'd space */
4044 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4045 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4047 I915_GTT_OFFSET_NONE,
4053 * From the Gunit register HAS:
4054 * The Gfx driver is expected to program this register and ensure
4055 * proper allocation within Gfx stolen memory. For example, this
4056 * register should be programmed such than the PCBR range does not
4057 * overlap with other ranges, such as the frame buffer, protected
4058 * memory, or any other relevant ranges.
4060 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4062 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4066 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4067 I915_WRITE(VLV_PCBR, pctx_paddr);
4070 dev_priv->vlv_pctx = pctx;
4073 static void valleyview_enable_rps(struct drm_device *dev)
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 struct intel_ring_buffer *ring;
4077 u32 gtfifodbg, val, rc6_mode = 0;
4080 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4082 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4083 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4085 I915_WRITE(GTFIFODBG, gtfifodbg);
4088 valleyview_setup_pctx(dev);
4090 /* If VLV, Forcewake all wells, else re-direct to regular path */
4091 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4093 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4094 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4095 I915_WRITE(GEN6_RP_UP_EI, 66000);
4096 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4098 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4100 I915_WRITE(GEN6_RP_CONTROL,
4101 GEN6_RP_MEDIA_TURBO |
4102 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4103 GEN6_RP_MEDIA_IS_GFX |
4105 GEN6_RP_UP_BUSY_AVG |
4106 GEN6_RP_DOWN_IDLE_CONT);
4108 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4109 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4110 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4112 for_each_ring(ring, dev_priv, i)
4113 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4115 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4117 /* allows RC6 residency counter to work */
4118 I915_WRITE(VLV_COUNTER_CONTROL,
4119 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4120 VLV_MEDIA_RC6_COUNT_EN |
4121 VLV_RENDER_RC6_COUNT_EN));
4122 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4123 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4125 intel_print_rc6_info(dev, rc6_mode);
4127 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4129 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4131 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4132 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4134 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4135 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4136 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
4137 dev_priv->rps.cur_delay);
4139 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4140 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4141 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4142 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
4143 dev_priv->rps.max_delay);
4145 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4146 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4147 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4148 dev_priv->rps.rpe_delay);
4150 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4151 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4152 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
4153 dev_priv->rps.min_delay);
4155 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4156 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4157 dev_priv->rps.rpe_delay);
4159 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4161 gen6_enable_rps_interrupts(dev);
4163 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4166 void ironlake_teardown_rc6(struct drm_device *dev)
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4170 if (dev_priv->ips.renderctx) {
4171 i915_gem_object_unpin(dev_priv->ips.renderctx);
4172 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4173 dev_priv->ips.renderctx = NULL;
4176 if (dev_priv->ips.pwrctx) {
4177 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4178 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4179 dev_priv->ips.pwrctx = NULL;
4183 static void ironlake_disable_rc6(struct drm_device *dev)
4185 struct drm_i915_private *dev_priv = dev->dev_private;
4187 if (I915_READ(PWRCTXA)) {
4188 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4189 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4190 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4193 I915_WRITE(PWRCTXA, 0);
4194 POSTING_READ(PWRCTXA);
4196 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4197 POSTING_READ(RSTDBYCTL);
4201 static int ironlake_setup_rc6(struct drm_device *dev)
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4205 if (dev_priv->ips.renderctx == NULL)
4206 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4207 if (!dev_priv->ips.renderctx)
4210 if (dev_priv->ips.pwrctx == NULL)
4211 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4212 if (!dev_priv->ips.pwrctx) {
4213 ironlake_teardown_rc6(dev);
4220 static void ironlake_enable_rc6(struct drm_device *dev)
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4224 bool was_interruptible;
4227 /* rc6 disabled by default due to repeated reports of hanging during
4230 if (!intel_enable_rc6(dev))
4233 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4235 ret = ironlake_setup_rc6(dev);
4239 was_interruptible = dev_priv->mm.interruptible;
4240 dev_priv->mm.interruptible = false;
4243 * GPU can automatically power down the render unit if given a page
4246 ret = intel_ring_begin(ring, 6);
4248 ironlake_teardown_rc6(dev);
4249 dev_priv->mm.interruptible = was_interruptible;
4253 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4254 intel_ring_emit(ring, MI_SET_CONTEXT);
4255 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4257 MI_SAVE_EXT_STATE_EN |
4258 MI_RESTORE_EXT_STATE_EN |
4259 MI_RESTORE_INHIBIT);
4260 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4261 intel_ring_emit(ring, MI_NOOP);
4262 intel_ring_emit(ring, MI_FLUSH);
4263 intel_ring_advance(ring);
4266 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4267 * does an implicit flush, combined with MI_FLUSH above, it should be
4268 * safe to assume that renderctx is valid
4270 ret = intel_ring_idle(ring);
4271 dev_priv->mm.interruptible = was_interruptible;
4273 DRM_ERROR("failed to enable ironlake power savings\n");
4274 ironlake_teardown_rc6(dev);
4278 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4279 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4281 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4284 static unsigned long intel_pxfreq(u32 vidfreq)
4287 int div = (vidfreq & 0x3f0000) >> 16;
4288 int post = (vidfreq & 0x3000) >> 12;
4289 int pre = (vidfreq & 0x7);
4294 freq = ((div * 133333) / ((1<<post) * pre));
4299 static const struct cparams {
4305 { 1, 1333, 301, 28664 },
4306 { 1, 1066, 294, 24460 },
4307 { 1, 800, 294, 25192 },
4308 { 0, 1333, 276, 27605 },
4309 { 0, 1066, 276, 27605 },
4310 { 0, 800, 231, 23784 },
4313 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4315 u64 total_count, diff, ret;
4316 u32 count1, count2, count3, m = 0, c = 0;
4317 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4320 assert_spin_locked(&mchdev_lock);
4322 diff1 = now - dev_priv->ips.last_time1;
4324 /* Prevent division-by-zero if we are asking too fast.
4325 * Also, we don't get interesting results if we are polling
4326 * faster than once in 10ms, so just return the saved value
4330 return dev_priv->ips.chipset_power;
4332 count1 = I915_READ(DMIEC);
4333 count2 = I915_READ(DDREC);
4334 count3 = I915_READ(CSIEC);
4336 total_count = count1 + count2 + count3;
4338 /* FIXME: handle per-counter overflow */
4339 if (total_count < dev_priv->ips.last_count1) {
4340 diff = ~0UL - dev_priv->ips.last_count1;
4341 diff += total_count;
4343 diff = total_count - dev_priv->ips.last_count1;
4346 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4347 if (cparams[i].i == dev_priv->ips.c_m &&
4348 cparams[i].t == dev_priv->ips.r_t) {
4355 diff = div_u64(diff, diff1);
4356 ret = ((m * diff) + c);
4357 ret = div_u64(ret, 10);
4359 dev_priv->ips.last_count1 = total_count;
4360 dev_priv->ips.last_time1 = now;
4362 dev_priv->ips.chipset_power = ret;
4367 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4371 if (dev_priv->info->gen != 5)
4374 spin_lock_irq(&mchdev_lock);
4376 val = __i915_chipset_val(dev_priv);
4378 spin_unlock_irq(&mchdev_lock);
4383 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4385 unsigned long m, x, b;
4388 tsfs = I915_READ(TSFS);
4390 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4391 x = I915_READ8(TR1);
4393 b = tsfs & TSFS_INTR_MASK;
4395 return ((m * x) / 127) - b;
4398 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4400 static const struct v_table {
4401 u16 vd; /* in .1 mil */
4402 u16 vm; /* in .1 mil */
4533 if (dev_priv->info->is_mobile)
4534 return v_table[pxvid].vm;
4536 return v_table[pxvid].vd;
4539 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4541 struct timespec now, diff1;
4543 unsigned long diffms;
4546 assert_spin_locked(&mchdev_lock);
4548 getrawmonotonic(&now);
4549 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4551 /* Don't divide by 0 */
4552 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4556 count = I915_READ(GFXEC);
4558 if (count < dev_priv->ips.last_count2) {
4559 diff = ~0UL - dev_priv->ips.last_count2;
4562 diff = count - dev_priv->ips.last_count2;
4565 dev_priv->ips.last_count2 = count;
4566 dev_priv->ips.last_time2 = now;
4568 /* More magic constants... */
4570 diff = div_u64(diff, diffms * 10);
4571 dev_priv->ips.gfx_power = diff;
4574 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4576 if (dev_priv->info->gen != 5)
4579 spin_lock_irq(&mchdev_lock);
4581 __i915_update_gfx_val(dev_priv);
4583 spin_unlock_irq(&mchdev_lock);
4586 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4588 unsigned long t, corr, state1, corr2, state2;
4591 assert_spin_locked(&mchdev_lock);
4593 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4594 pxvid = (pxvid >> 24) & 0x7f;
4595 ext_v = pvid_to_extvid(dev_priv, pxvid);
4599 t = i915_mch_val(dev_priv);
4601 /* Revel in the empirically derived constants */
4603 /* Correction factor in 1/100000 units */
4605 corr = ((t * 2349) + 135940);
4607 corr = ((t * 964) + 29317);
4609 corr = ((t * 301) + 1004);
4611 corr = corr * ((150142 * state1) / 10000 - 78642);
4613 corr2 = (corr * dev_priv->ips.corr);
4615 state2 = (corr2 * state1) / 10000;
4616 state2 /= 100; /* convert to mW */
4618 __i915_update_gfx_val(dev_priv);
4620 return dev_priv->ips.gfx_power + state2;
4623 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4627 if (dev_priv->info->gen != 5)
4630 spin_lock_irq(&mchdev_lock);
4632 val = __i915_gfx_val(dev_priv);
4634 spin_unlock_irq(&mchdev_lock);
4640 * i915_read_mch_val - return value for IPS use
4642 * Calculate and return a value for the IPS driver to use when deciding whether
4643 * we have thermal and power headroom to increase CPU or GPU power budget.
4645 unsigned long i915_read_mch_val(void)
4647 struct drm_i915_private *dev_priv;
4648 unsigned long chipset_val, graphics_val, ret = 0;
4650 spin_lock_irq(&mchdev_lock);
4653 dev_priv = i915_mch_dev;
4655 chipset_val = __i915_chipset_val(dev_priv);
4656 graphics_val = __i915_gfx_val(dev_priv);
4658 ret = chipset_val + graphics_val;
4661 spin_unlock_irq(&mchdev_lock);
4665 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4668 * i915_gpu_raise - raise GPU frequency limit
4670 * Raise the limit; IPS indicates we have thermal headroom.
4672 bool i915_gpu_raise(void)
4674 struct drm_i915_private *dev_priv;
4677 spin_lock_irq(&mchdev_lock);
4678 if (!i915_mch_dev) {
4682 dev_priv = i915_mch_dev;
4684 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4685 dev_priv->ips.max_delay--;
4688 spin_unlock_irq(&mchdev_lock);
4692 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4695 * i915_gpu_lower - lower GPU frequency limit
4697 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4698 * frequency maximum.
4700 bool i915_gpu_lower(void)
4702 struct drm_i915_private *dev_priv;
4705 spin_lock_irq(&mchdev_lock);
4706 if (!i915_mch_dev) {
4710 dev_priv = i915_mch_dev;
4712 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4713 dev_priv->ips.max_delay++;
4716 spin_unlock_irq(&mchdev_lock);
4720 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4723 * i915_gpu_busy - indicate GPU business to IPS
4725 * Tell the IPS driver whether or not the GPU is busy.
4727 bool i915_gpu_busy(void)
4729 struct drm_i915_private *dev_priv;
4730 struct intel_ring_buffer *ring;
4734 spin_lock_irq(&mchdev_lock);
4737 dev_priv = i915_mch_dev;
4739 for_each_ring(ring, dev_priv, i)
4740 ret |= !list_empty(&ring->request_list);
4743 spin_unlock_irq(&mchdev_lock);
4747 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4750 * i915_gpu_turbo_disable - disable graphics turbo
4752 * Disable graphics turbo by resetting the max frequency and setting the
4753 * current frequency to the default.
4755 bool i915_gpu_turbo_disable(void)
4757 struct drm_i915_private *dev_priv;
4760 spin_lock_irq(&mchdev_lock);
4761 if (!i915_mch_dev) {
4765 dev_priv = i915_mch_dev;
4767 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4769 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4773 spin_unlock_irq(&mchdev_lock);
4777 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4780 * Tells the intel_ips driver that the i915 driver is now loaded, if
4781 * IPS got loaded first.
4783 * This awkward dance is so that neither module has to depend on the
4784 * other in order for IPS to do the appropriate communication of
4785 * GPU turbo limits to i915.
4788 ips_ping_for_i915_load(void)
4792 link = symbol_get(ips_link_to_i915_driver);
4795 symbol_put(ips_link_to_i915_driver);
4799 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4801 /* We only register the i915 ips part with intel-ips once everything is
4802 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4803 spin_lock_irq(&mchdev_lock);
4804 i915_mch_dev = dev_priv;
4805 spin_unlock_irq(&mchdev_lock);
4807 ips_ping_for_i915_load();
4810 void intel_gpu_ips_teardown(void)
4812 spin_lock_irq(&mchdev_lock);
4813 i915_mch_dev = NULL;
4814 spin_unlock_irq(&mchdev_lock);
4816 static void intel_init_emon(struct drm_device *dev)
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4823 /* Disable to program */
4827 /* Program energy weights for various events */
4828 I915_WRITE(SDEW, 0x15040d00);
4829 I915_WRITE(CSIEW0, 0x007f0000);
4830 I915_WRITE(CSIEW1, 0x1e220004);
4831 I915_WRITE(CSIEW2, 0x04000004);
4833 for (i = 0; i < 5; i++)
4834 I915_WRITE(PEW + (i * 4), 0);
4835 for (i = 0; i < 3; i++)
4836 I915_WRITE(DEW + (i * 4), 0);
4838 /* Program P-state weights to account for frequency power adjustment */
4839 for (i = 0; i < 16; i++) {
4840 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4841 unsigned long freq = intel_pxfreq(pxvidfreq);
4842 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4847 val *= (freq / 1000);
4849 val /= (127*127*900);
4851 DRM_ERROR("bad pxval: %ld\n", val);
4854 /* Render standby states get 0 weight */
4858 for (i = 0; i < 4; i++) {
4859 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4860 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4861 I915_WRITE(PXW + (i * 4), val);
4864 /* Adjust magic regs to magic values (more experimental results) */
4865 I915_WRITE(OGW0, 0);
4866 I915_WRITE(OGW1, 0);
4867 I915_WRITE(EG0, 0x00007f00);
4868 I915_WRITE(EG1, 0x0000000e);
4869 I915_WRITE(EG2, 0x000e0000);
4870 I915_WRITE(EG3, 0x68000300);
4871 I915_WRITE(EG4, 0x42000000);
4872 I915_WRITE(EG5, 0x00140031);
4876 for (i = 0; i < 8; i++)
4877 I915_WRITE(PXWL + (i * 4), 0);
4879 /* Enable PMON + select events */
4880 I915_WRITE(ECR, 0x80000019);
4882 lcfuse = I915_READ(LCFUSE02);
4884 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4887 void intel_disable_gt_powersave(struct drm_device *dev)
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4891 /* Interrupts should be disabled already to avoid re-arming. */
4892 WARN_ON(dev->irq_enabled);
4894 if (IS_IRONLAKE_M(dev)) {
4895 ironlake_disable_drps(dev);
4896 ironlake_disable_rc6(dev);
4897 } else if (INTEL_INFO(dev)->gen >= 6) {
4898 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4899 cancel_work_sync(&dev_priv->rps.work);
4900 mutex_lock(&dev_priv->rps.hw_lock);
4901 if (IS_VALLEYVIEW(dev))
4902 valleyview_disable_rps(dev);
4904 gen6_disable_rps(dev);
4905 dev_priv->rps.enabled = false;
4906 mutex_unlock(&dev_priv->rps.hw_lock);
4910 static void intel_gen6_powersave_work(struct work_struct *work)
4912 struct drm_i915_private *dev_priv =
4913 container_of(work, struct drm_i915_private,
4914 rps.delayed_resume_work.work);
4915 struct drm_device *dev = dev_priv->dev;
4917 mutex_lock(&dev_priv->rps.hw_lock);
4919 if (IS_VALLEYVIEW(dev)) {
4920 valleyview_enable_rps(dev);
4921 } else if (IS_BROADWELL(dev)) {
4922 gen8_enable_rps(dev);
4923 gen6_update_ring_freq(dev);
4925 gen6_enable_rps(dev);
4926 gen6_update_ring_freq(dev);
4928 dev_priv->rps.enabled = true;
4929 mutex_unlock(&dev_priv->rps.hw_lock);
4932 void intel_enable_gt_powersave(struct drm_device *dev)
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4936 if (IS_IRONLAKE_M(dev)) {
4937 ironlake_enable_drps(dev);
4938 ironlake_enable_rc6(dev);
4939 intel_init_emon(dev);
4940 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4942 * PCU communication is slow and this doesn't need to be
4943 * done at any specific time, so do this out of our fast path
4944 * to make resume and init faster.
4946 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4947 round_jiffies_up_relative(HZ));
4951 static void ibx_init_clock_gating(struct drm_device *dev)
4953 struct drm_i915_private *dev_priv = dev->dev_private;
4956 * On Ibex Peak and Cougar Point, we need to disable clock
4957 * gating for the panel power sequencer or it will fail to
4958 * start up when no ports are active.
4960 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4963 static void g4x_disable_trickle_feed(struct drm_device *dev)
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4968 for_each_pipe(pipe) {
4969 I915_WRITE(DSPCNTR(pipe),
4970 I915_READ(DSPCNTR(pipe)) |
4971 DISPPLANE_TRICKLE_FEED_DISABLE);
4972 intel_flush_primary_plane(dev_priv, pipe);
4976 static void ironlake_init_clock_gating(struct drm_device *dev)
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4983 * WaFbcDisableDpfcClockGating:ilk
4985 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4986 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4987 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4989 I915_WRITE(PCH_3DCGDIS0,
4990 MARIUNIT_CLOCK_GATE_DISABLE |
4991 SVSMUNIT_CLOCK_GATE_DISABLE);
4992 I915_WRITE(PCH_3DCGDIS1,
4993 VFMUNIT_CLOCK_GATE_DISABLE);
4996 * According to the spec the following bits should be set in
4997 * order to enable memory self-refresh
4998 * The bit 22/21 of 0x42004
4999 * The bit 5 of 0x42020
5000 * The bit 15 of 0x45000
5002 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5003 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5004 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5005 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5006 I915_WRITE(DISP_ARB_CTL,
5007 (I915_READ(DISP_ARB_CTL) |
5009 I915_WRITE(WM3_LP_ILK, 0);
5010 I915_WRITE(WM2_LP_ILK, 0);
5011 I915_WRITE(WM1_LP_ILK, 0);
5014 * Based on the document from hardware guys the following bits
5015 * should be set unconditionally in order to enable FBC.
5016 * The bit 22 of 0x42000
5017 * The bit 22 of 0x42004
5018 * The bit 7,8,9 of 0x42020.
5020 if (IS_IRONLAKE_M(dev)) {
5021 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5022 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5023 I915_READ(ILK_DISPLAY_CHICKEN1) |
5025 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5026 I915_READ(ILK_DISPLAY_CHICKEN2) |
5030 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5032 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5033 I915_READ(ILK_DISPLAY_CHICKEN2) |
5034 ILK_ELPIN_409_SELECT);
5035 I915_WRITE(_3D_CHICKEN2,
5036 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5037 _3D_CHICKEN2_WM_READ_PIPELINED);
5039 /* WaDisableRenderCachePipelinedFlush:ilk */
5040 I915_WRITE(CACHE_MODE_0,
5041 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5043 g4x_disable_trickle_feed(dev);
5045 ibx_init_clock_gating(dev);
5048 static void cpt_init_clock_gating(struct drm_device *dev)
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5055 * On Ibex Peak and Cougar Point, we need to disable clock
5056 * gating for the panel power sequencer or it will fail to
5057 * start up when no ports are active.
5059 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5060 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5061 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5062 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5063 DPLS_EDP_PPS_FIX_DIS);
5064 /* The below fixes the weird display corruption, a few pixels shifted
5065 * downward, on (only) LVDS of some HP laptops with IVY.
5067 for_each_pipe(pipe) {
5068 val = I915_READ(TRANS_CHICKEN2(pipe));
5069 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5070 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5071 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5072 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5073 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5074 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5075 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5076 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5078 /* WADP0ClockGatingDisable */
5079 for_each_pipe(pipe) {
5080 I915_WRITE(TRANS_CHICKEN1(pipe),
5081 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5085 static void gen6_check_mch_setup(struct drm_device *dev)
5087 struct drm_i915_private *dev_priv = dev->dev_private;
5090 tmp = I915_READ(MCH_SSKPD);
5091 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5092 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5093 DRM_INFO("This can cause pipe underruns and display issues.\n");
5094 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5098 static void gen6_init_clock_gating(struct drm_device *dev)
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5103 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5105 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5106 I915_READ(ILK_DISPLAY_CHICKEN2) |
5107 ILK_ELPIN_409_SELECT);
5109 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5110 I915_WRITE(_3D_CHICKEN,
5111 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5113 /* WaSetupGtModeTdRowDispatch:snb */
5114 if (IS_SNB_GT1(dev))
5115 I915_WRITE(GEN6_GT_MODE,
5116 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5118 I915_WRITE(WM3_LP_ILK, 0);
5119 I915_WRITE(WM2_LP_ILK, 0);
5120 I915_WRITE(WM1_LP_ILK, 0);
5122 I915_WRITE(CACHE_MODE_0,
5123 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5125 I915_WRITE(GEN6_UCGCTL1,
5126 I915_READ(GEN6_UCGCTL1) |
5127 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5128 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5130 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5131 * gating disable must be set. Failure to set it results in
5132 * flickering pixels due to Z write ordering failures after
5133 * some amount of runtime in the Mesa "fire" demo, and Unigine
5134 * Sanctuary and Tropics, and apparently anything else with
5135 * alpha test or pixel discard.
5137 * According to the spec, bit 11 (RCCUNIT) must also be set,
5138 * but we didn't debug actual testcases to find it out.
5140 * Also apply WaDisableVDSUnitClockGating:snb and
5141 * WaDisableRCPBUnitClockGating:snb.
5143 I915_WRITE(GEN6_UCGCTL2,
5144 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5145 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5146 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5148 /* Bspec says we need to always set all mask bits. */
5149 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5150 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5153 * According to the spec the following bits should be
5154 * set in order to enable memory self-refresh and fbc:
5155 * The bit21 and bit22 of 0x42000
5156 * The bit21 and bit22 of 0x42004
5157 * The bit5 and bit7 of 0x42020
5158 * The bit14 of 0x70180
5159 * The bit14 of 0x71180
5161 * WaFbcAsynchFlipDisableFbcQueue:snb
5163 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5164 I915_READ(ILK_DISPLAY_CHICKEN1) |
5165 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5166 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5167 I915_READ(ILK_DISPLAY_CHICKEN2) |
5168 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5169 I915_WRITE(ILK_DSPCLK_GATE_D,
5170 I915_READ(ILK_DSPCLK_GATE_D) |
5171 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5172 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5174 g4x_disable_trickle_feed(dev);
5176 /* The default value should be 0x200 according to docs, but the two
5177 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5178 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5179 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5181 cpt_init_clock_gating(dev);
5183 gen6_check_mch_setup(dev);
5186 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5188 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5190 reg &= ~GEN7_FF_SCHED_MASK;
5191 reg |= GEN7_FF_TS_SCHED_HW;
5192 reg |= GEN7_FF_VS_SCHED_HW;
5193 reg |= GEN7_FF_DS_SCHED_HW;
5195 if (IS_HASWELL(dev_priv->dev))
5196 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5198 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5201 static void lpt_init_clock_gating(struct drm_device *dev)
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5206 * TODO: this bit should only be enabled when really needed, then
5207 * disabled when not needed anymore in order to save power.
5209 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5210 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5211 I915_READ(SOUTH_DSPCLK_GATE_D) |
5212 PCH_LP_PARTITION_LEVEL_DISABLE);
5214 /* WADPOClockGatingDisable:hsw */
5215 I915_WRITE(_TRANSA_CHICKEN1,
5216 I915_READ(_TRANSA_CHICKEN1) |
5217 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5220 static void lpt_suspend_hw(struct drm_device *dev)
5222 struct drm_i915_private *dev_priv = dev->dev_private;
5224 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5225 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5227 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5228 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5232 static void gen8_init_clock_gating(struct drm_device *dev)
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5237 I915_WRITE(WM3_LP_ILK, 0);
5238 I915_WRITE(WM2_LP_ILK, 0);
5239 I915_WRITE(WM1_LP_ILK, 0);
5241 /* FIXME(BDW): Check all the w/a, some might only apply to
5242 * pre-production hw. */
5244 WARN(!i915_preliminary_hw_support,
5245 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5246 I915_WRITE(HALF_SLICE_CHICKEN3,
5247 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5248 I915_WRITE(HALF_SLICE_CHICKEN3,
5249 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5250 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5252 I915_WRITE(_3D_CHICKEN3,
5253 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5255 I915_WRITE(COMMON_SLICE_CHICKEN2,
5256 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5258 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5259 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5261 /* WaSwitchSolVfFArbitrationPriority */
5262 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5264 /* WaPsrDPAMaskVBlankInSRD */
5265 I915_WRITE(CHICKEN_PAR1_1,
5266 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5268 /* WaPsrDPRSUnmaskVBlankInSRD */
5270 I915_WRITE(CHICKEN_PIPESL_1(i),
5271 I915_READ(CHICKEN_PIPESL_1(i) |
5272 DPRS_MASK_VBLANK_SRD));
5276 static void haswell_init_clock_gating(struct drm_device *dev)
5278 struct drm_i915_private *dev_priv = dev->dev_private;
5280 I915_WRITE(WM3_LP_ILK, 0);
5281 I915_WRITE(WM2_LP_ILK, 0);
5282 I915_WRITE(WM1_LP_ILK, 0);
5284 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5285 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5287 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5289 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5290 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5291 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5293 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5294 I915_WRITE(GEN7_L3CNTLREG1,
5295 GEN7_WA_FOR_GEN7_L3_CONTROL);
5296 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5297 GEN7_WA_L3_CHICKEN_MODE);
5299 /* L3 caching of data atomics doesn't work -- disable it. */
5300 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5301 I915_WRITE(HSW_ROW_CHICKEN3,
5302 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5304 /* This is required by WaCatErrorRejectionIssue:hsw */
5305 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5306 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5307 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5309 /* WaVSRefCountFullforceMissDisable:hsw */
5310 gen7_setup_fixed_func_scheduler(dev_priv);
5312 /* WaDisable4x2SubspanOptimization:hsw */
5313 I915_WRITE(CACHE_MODE_1,
5314 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5316 /* WaSwitchSolVfFArbitrationPriority:hsw */
5317 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5319 /* WaRsPkgCStateDisplayPMReq:hsw */
5320 I915_WRITE(CHICKEN_PAR1_1,
5321 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5323 lpt_init_clock_gating(dev);
5326 static void ivybridge_init_clock_gating(struct drm_device *dev)
5328 struct drm_i915_private *dev_priv = dev->dev_private;
5331 I915_WRITE(WM3_LP_ILK, 0);
5332 I915_WRITE(WM2_LP_ILK, 0);
5333 I915_WRITE(WM1_LP_ILK, 0);
5335 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5337 /* WaDisableEarlyCull:ivb */
5338 I915_WRITE(_3D_CHICKEN3,
5339 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5341 /* WaDisableBackToBackFlipFix:ivb */
5342 I915_WRITE(IVB_CHICKEN3,
5343 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5344 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5346 /* WaDisablePSDDualDispatchEnable:ivb */
5347 if (IS_IVB_GT1(dev))
5348 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5349 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5351 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5352 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5354 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5355 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5356 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5358 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5359 I915_WRITE(GEN7_L3CNTLREG1,
5360 GEN7_WA_FOR_GEN7_L3_CONTROL);
5361 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5362 GEN7_WA_L3_CHICKEN_MODE);
5363 if (IS_IVB_GT1(dev))
5364 I915_WRITE(GEN7_ROW_CHICKEN2,
5365 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5367 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5368 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5371 /* WaForceL3Serialization:ivb */
5372 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5373 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5375 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5376 * gating disable must be set. Failure to set it results in
5377 * flickering pixels due to Z write ordering failures after
5378 * some amount of runtime in the Mesa "fire" demo, and Unigine
5379 * Sanctuary and Tropics, and apparently anything else with
5380 * alpha test or pixel discard.
5382 * According to the spec, bit 11 (RCCUNIT) must also be set,
5383 * but we didn't debug actual testcases to find it out.
5385 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5386 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5388 I915_WRITE(GEN6_UCGCTL2,
5389 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5390 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5392 /* This is required by WaCatErrorRejectionIssue:ivb */
5393 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5394 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5395 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5397 g4x_disable_trickle_feed(dev);
5399 /* WaVSRefCountFullforceMissDisable:ivb */
5400 gen7_setup_fixed_func_scheduler(dev_priv);
5402 /* WaDisable4x2SubspanOptimization:ivb */
5403 I915_WRITE(CACHE_MODE_1,
5404 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5406 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5407 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5408 snpcr |= GEN6_MBC_SNPCR_MED;
5409 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5411 if (!HAS_PCH_NOP(dev))
5412 cpt_init_clock_gating(dev);
5414 gen6_check_mch_setup(dev);
5417 static void valleyview_init_clock_gating(struct drm_device *dev)
5419 struct drm_i915_private *dev_priv = dev->dev_private;
5422 mutex_lock(&dev_priv->rps.hw_lock);
5423 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5424 mutex_unlock(&dev_priv->rps.hw_lock);
5425 switch ((val >> 6) & 3) {
5427 dev_priv->mem_freq = 800;
5430 dev_priv->mem_freq = 1066;
5433 dev_priv->mem_freq = 1333;
5436 dev_priv->mem_freq = 1333;
5439 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5441 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5443 /* WaDisableEarlyCull:vlv */
5444 I915_WRITE(_3D_CHICKEN3,
5445 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5447 /* WaDisableBackToBackFlipFix:vlv */
5448 I915_WRITE(IVB_CHICKEN3,
5449 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5450 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5452 /* WaDisablePSDDualDispatchEnable:vlv */
5453 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5454 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5455 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5457 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5458 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5459 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5461 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5462 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5463 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5465 /* WaForceL3Serialization:vlv */
5466 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5467 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5469 /* WaDisableDopClockGating:vlv */
5470 I915_WRITE(GEN7_ROW_CHICKEN2,
5471 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5473 /* This is required by WaCatErrorRejectionIssue:vlv */
5474 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5475 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5476 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5478 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5479 * gating disable must be set. Failure to set it results in
5480 * flickering pixels due to Z write ordering failures after
5481 * some amount of runtime in the Mesa "fire" demo, and Unigine
5482 * Sanctuary and Tropics, and apparently anything else with
5483 * alpha test or pixel discard.
5485 * According to the spec, bit 11 (RCCUNIT) must also be set,
5486 * but we didn't debug actual testcases to find it out.
5488 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5489 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5491 * Also apply WaDisableVDSUnitClockGating:vlv and
5492 * WaDisableRCPBUnitClockGating:vlv.
5494 I915_WRITE(GEN6_UCGCTL2,
5495 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5496 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5497 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5498 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5499 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5501 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5503 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5505 I915_WRITE(CACHE_MODE_1,
5506 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5509 * WaDisableVLVClockGating_VBIIssue:vlv
5510 * Disable clock gating on th GCFG unit to prevent a delay
5511 * in the reporting of vblank events.
5513 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5515 /* Conservative clock gating settings for now */
5516 I915_WRITE(0x9400, 0xffffffff);
5517 I915_WRITE(0x9404, 0xffffffff);
5518 I915_WRITE(0x9408, 0xffffffff);
5519 I915_WRITE(0x940c, 0xffffffff);
5520 I915_WRITE(0x9410, 0xffffffff);
5521 I915_WRITE(0x9414, 0xffffffff);
5522 I915_WRITE(0x9418, 0xffffffff);
5525 static void g4x_init_clock_gating(struct drm_device *dev)
5527 struct drm_i915_private *dev_priv = dev->dev_private;
5528 uint32_t dspclk_gate;
5530 I915_WRITE(RENCLK_GATE_D1, 0);
5531 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5532 GS_UNIT_CLOCK_GATE_DISABLE |
5533 CL_UNIT_CLOCK_GATE_DISABLE);
5534 I915_WRITE(RAMCLK_GATE_D, 0);
5535 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5536 OVRUNIT_CLOCK_GATE_DISABLE |
5537 OVCUNIT_CLOCK_GATE_DISABLE;
5539 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5540 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5542 /* WaDisableRenderCachePipelinedFlush */
5543 I915_WRITE(CACHE_MODE_0,
5544 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5546 g4x_disable_trickle_feed(dev);
5549 static void crestline_init_clock_gating(struct drm_device *dev)
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5553 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5554 I915_WRITE(RENCLK_GATE_D2, 0);
5555 I915_WRITE(DSPCLK_GATE_D, 0);
5556 I915_WRITE(RAMCLK_GATE_D, 0);
5557 I915_WRITE16(DEUC, 0);
5558 I915_WRITE(MI_ARB_STATE,
5559 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5562 static void broadwater_init_clock_gating(struct drm_device *dev)
5564 struct drm_i915_private *dev_priv = dev->dev_private;
5566 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5567 I965_RCC_CLOCK_GATE_DISABLE |
5568 I965_RCPB_CLOCK_GATE_DISABLE |
5569 I965_ISC_CLOCK_GATE_DISABLE |
5570 I965_FBC_CLOCK_GATE_DISABLE);
5571 I915_WRITE(RENCLK_GATE_D2, 0);
5572 I915_WRITE(MI_ARB_STATE,
5573 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5576 static void gen3_init_clock_gating(struct drm_device *dev)
5578 struct drm_i915_private *dev_priv = dev->dev_private;
5579 u32 dstate = I915_READ(D_STATE);
5581 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5582 DSTATE_DOT_CLOCK_GATING;
5583 I915_WRITE(D_STATE, dstate);
5585 if (IS_PINEVIEW(dev))
5586 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5588 /* IIR "flip pending" means done if this bit is set */
5589 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5592 static void i85x_init_clock_gating(struct drm_device *dev)
5594 struct drm_i915_private *dev_priv = dev->dev_private;
5596 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5599 static void i830_init_clock_gating(struct drm_device *dev)
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5603 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5606 void intel_init_clock_gating(struct drm_device *dev)
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5610 dev_priv->display.init_clock_gating(dev);
5613 void intel_suspend_hw(struct drm_device *dev)
5615 if (HAS_PCH_LPT(dev))
5616 lpt_suspend_hw(dev);
5619 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5621 i < (power_domains)->power_well_count && \
5622 ((power_well) = &(power_domains)->power_wells[i]); \
5624 if ((power_well)->domains & (domain_mask))
5626 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5627 for (i = (power_domains)->power_well_count - 1; \
5628 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5630 if ((power_well)->domains & (domain_mask))
5633 * We should only use the power well if we explicitly asked the hardware to
5634 * enable it, so check if it's enabled and also check if we've requested it to
5637 static bool hsw_power_well_enabled(struct drm_device *dev,
5638 struct i915_power_well *power_well)
5640 struct drm_i915_private *dev_priv = dev->dev_private;
5642 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5643 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5646 bool intel_display_power_enabled_sw(struct drm_device *dev,
5647 enum intel_display_power_domain domain)
5649 struct drm_i915_private *dev_priv = dev->dev_private;
5650 struct i915_power_domains *power_domains;
5652 power_domains = &dev_priv->power_domains;
5654 return power_domains->domain_use_count[domain];
5657 bool intel_display_power_enabled(struct drm_device *dev,
5658 enum intel_display_power_domain domain)
5660 struct drm_i915_private *dev_priv = dev->dev_private;
5661 struct i915_power_domains *power_domains;
5662 struct i915_power_well *power_well;
5666 power_domains = &dev_priv->power_domains;
5670 mutex_lock(&power_domains->lock);
5671 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5672 if (power_well->always_on)
5675 if (!power_well->is_enabled(dev, power_well)) {
5680 mutex_unlock(&power_domains->lock);
5685 static void hsw_set_power_well(struct drm_device *dev,
5686 struct i915_power_well *power_well, bool enable)
5688 struct drm_i915_private *dev_priv = dev->dev_private;
5689 bool is_enabled, enable_requested;
5690 unsigned long irqflags;
5693 WARN_ON(dev_priv->pc8.enabled);
5695 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5696 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5697 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5700 if (!enable_requested)
5701 I915_WRITE(HSW_PWR_WELL_DRIVER,
5702 HSW_PWR_WELL_ENABLE_REQUEST);
5705 DRM_DEBUG_KMS("Enabling power well\n");
5706 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5707 HSW_PWR_WELL_STATE_ENABLED), 20))
5708 DRM_ERROR("Timeout enabling power well\n");
5711 if (IS_BROADWELL(dev)) {
5712 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5713 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5714 dev_priv->de_irq_mask[PIPE_B]);
5715 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5716 ~dev_priv->de_irq_mask[PIPE_B] |
5718 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5719 dev_priv->de_irq_mask[PIPE_C]);
5720 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5721 ~dev_priv->de_irq_mask[PIPE_C] |
5723 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5724 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5727 if (enable_requested) {
5730 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5731 POSTING_READ(HSW_PWR_WELL_DRIVER);
5732 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5735 * After this, the registers on the pipes that are part
5736 * of the power well will become zero, so we have to
5737 * adjust our counters according to that.
5739 * FIXME: Should we do this in general in
5740 * drm_vblank_post_modeset?
5742 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5745 dev->vblank[p].last = 0;
5746 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5751 static void __intel_power_well_get(struct drm_device *dev,
5752 struct i915_power_well *power_well)
5754 struct drm_i915_private *dev_priv = dev->dev_private;
5756 if (!power_well->count++ && power_well->set) {
5757 hsw_disable_package_c8(dev_priv);
5758 power_well->set(dev, power_well, true);
5762 static void __intel_power_well_put(struct drm_device *dev,
5763 struct i915_power_well *power_well)
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5767 WARN_ON(!power_well->count);
5769 if (!--power_well->count && power_well->set &&
5770 i915_disable_power_well) {
5771 power_well->set(dev, power_well, false);
5772 hsw_enable_package_c8(dev_priv);
5776 void intel_display_power_get(struct drm_device *dev,
5777 enum intel_display_power_domain domain)
5779 struct drm_i915_private *dev_priv = dev->dev_private;
5780 struct i915_power_domains *power_domains;
5781 struct i915_power_well *power_well;
5784 power_domains = &dev_priv->power_domains;
5786 mutex_lock(&power_domains->lock);
5788 for_each_power_well(i, power_well, BIT(domain), power_domains)
5789 __intel_power_well_get(dev, power_well);
5791 power_domains->domain_use_count[domain]++;
5793 mutex_unlock(&power_domains->lock);
5796 void intel_display_power_put(struct drm_device *dev,
5797 enum intel_display_power_domain domain)
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800 struct i915_power_domains *power_domains;
5801 struct i915_power_well *power_well;
5804 power_domains = &dev_priv->power_domains;
5806 mutex_lock(&power_domains->lock);
5808 WARN_ON(!power_domains->domain_use_count[domain]);
5809 power_domains->domain_use_count[domain]--;
5811 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5812 __intel_power_well_put(dev, power_well);
5814 mutex_unlock(&power_domains->lock);
5817 static struct i915_power_domains *hsw_pwr;
5819 /* Display audio driver power well request */
5820 void i915_request_power_well(void)
5822 struct drm_i915_private *dev_priv;
5824 if (WARN_ON(!hsw_pwr))
5827 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5829 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5831 EXPORT_SYMBOL_GPL(i915_request_power_well);
5833 /* Display audio driver power well release */
5834 void i915_release_power_well(void)
5836 struct drm_i915_private *dev_priv;
5838 if (WARN_ON(!hsw_pwr))
5841 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5843 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5845 EXPORT_SYMBOL_GPL(i915_release_power_well);
5847 static struct i915_power_well i9xx_always_on_power_well[] = {
5849 .name = "always-on",
5851 .domains = POWER_DOMAIN_MASK,
5855 static struct i915_power_well hsw_power_wells[] = {
5857 .name = "always-on",
5859 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5863 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5864 .is_enabled = hsw_power_well_enabled,
5865 .set = hsw_set_power_well,
5869 static struct i915_power_well bdw_power_wells[] = {
5871 .name = "always-on",
5873 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5877 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5878 .is_enabled = hsw_power_well_enabled,
5879 .set = hsw_set_power_well,
5883 #define set_power_wells(power_domains, __power_wells) ({ \
5884 (power_domains)->power_wells = (__power_wells); \
5885 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5888 int intel_power_domains_init(struct drm_device *dev)
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5893 mutex_init(&power_domains->lock);
5896 * The enabling order will be from lower to higher indexed wells,
5897 * the disabling order is reversed.
5899 if (IS_HASWELL(dev)) {
5900 set_power_wells(power_domains, hsw_power_wells);
5901 hsw_pwr = power_domains;
5902 } else if (IS_BROADWELL(dev)) {
5903 set_power_wells(power_domains, bdw_power_wells);
5904 hsw_pwr = power_domains;
5906 set_power_wells(power_domains, i9xx_always_on_power_well);
5912 void intel_power_domains_remove(struct drm_device *dev)
5917 static void intel_power_domains_resume(struct drm_device *dev)
5919 struct drm_i915_private *dev_priv = dev->dev_private;
5920 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5921 struct i915_power_well *power_well;
5924 mutex_lock(&power_domains->lock);
5925 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5926 if (power_well->set)
5927 power_well->set(dev, power_well, power_well->count > 0);
5929 mutex_unlock(&power_domains->lock);
5933 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5934 * when not needed anymore. We have 4 registers that can request the power well
5935 * to be enabled, and it will only be disabled if none of the registers is
5936 * requesting it to be enabled.
5938 void intel_power_domains_init_hw(struct drm_device *dev)
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5942 /* For now, we need the power well to be always enabled. */
5943 intel_display_set_init_power(dev, true);
5944 intel_power_domains_resume(dev);
5946 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5949 /* We're taking over the BIOS, so clear any requests made by it since
5950 * the driver is in charge now. */
5951 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5952 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5955 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5956 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5958 hsw_disable_package_c8(dev_priv);
5961 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5963 hsw_enable_package_c8(dev_priv);
5966 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5968 struct drm_device *dev = dev_priv->dev;
5969 struct device *device = &dev->pdev->dev;
5971 if (!HAS_RUNTIME_PM(dev))
5974 pm_runtime_get_sync(device);
5975 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5978 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5980 struct drm_device *dev = dev_priv->dev;
5981 struct device *device = &dev->pdev->dev;
5983 if (!HAS_RUNTIME_PM(dev))
5986 pm_runtime_mark_last_busy(device);
5987 pm_runtime_put_autosuspend(device);
5990 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5992 struct drm_device *dev = dev_priv->dev;
5993 struct device *device = &dev->pdev->dev;
5995 dev_priv->pm.suspended = false;
5997 if (!HAS_RUNTIME_PM(dev))
6000 pm_runtime_set_active(device);
6002 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6003 pm_runtime_mark_last_busy(device);
6004 pm_runtime_use_autosuspend(device);
6007 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6009 struct drm_device *dev = dev_priv->dev;
6010 struct device *device = &dev->pdev->dev;
6012 if (!HAS_RUNTIME_PM(dev))
6015 /* Make sure we're not suspended first. */
6016 pm_runtime_get_sync(device);
6017 pm_runtime_disable(device);
6020 /* Set up chip specific power management-related functions */
6021 void intel_init_pm(struct drm_device *dev)
6023 struct drm_i915_private *dev_priv = dev->dev_private;
6025 if (I915_HAS_FBC(dev)) {
6026 if (INTEL_INFO(dev)->gen >= 7) {
6027 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6028 dev_priv->display.enable_fbc = gen7_enable_fbc;
6029 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6030 } else if (INTEL_INFO(dev)->gen >= 5) {
6031 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6032 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6033 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6034 } else if (IS_GM45(dev)) {
6035 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6036 dev_priv->display.enable_fbc = g4x_enable_fbc;
6037 dev_priv->display.disable_fbc = g4x_disable_fbc;
6039 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6040 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6041 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6046 if (IS_PINEVIEW(dev))
6047 i915_pineview_get_mem_freq(dev);
6048 else if (IS_GEN5(dev))
6049 i915_ironlake_get_mem_freq(dev);
6051 /* For FIFO watermark updates */
6052 if (HAS_PCH_SPLIT(dev)) {
6053 intel_setup_wm_latency(dev);
6056 if (dev_priv->wm.pri_latency[1] &&
6057 dev_priv->wm.spr_latency[1] &&
6058 dev_priv->wm.cur_latency[1])
6059 dev_priv->display.update_wm = ironlake_update_wm;
6061 DRM_DEBUG_KMS("Failed to get proper latency. "
6063 dev_priv->display.update_wm = NULL;
6065 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6066 } else if (IS_GEN6(dev)) {
6067 if (dev_priv->wm.pri_latency[0] &&
6068 dev_priv->wm.spr_latency[0] &&
6069 dev_priv->wm.cur_latency[0]) {
6070 dev_priv->display.update_wm = sandybridge_update_wm;
6071 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6073 DRM_DEBUG_KMS("Failed to read display plane latency. "
6075 dev_priv->display.update_wm = NULL;
6077 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6078 } else if (IS_IVYBRIDGE(dev)) {
6079 if (dev_priv->wm.pri_latency[0] &&
6080 dev_priv->wm.spr_latency[0] &&
6081 dev_priv->wm.cur_latency[0]) {
6082 dev_priv->display.update_wm = ivybridge_update_wm;
6083 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6085 DRM_DEBUG_KMS("Failed to read display plane latency. "
6087 dev_priv->display.update_wm = NULL;
6089 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6090 } else if (IS_HASWELL(dev)) {
6091 if (dev_priv->wm.pri_latency[0] &&
6092 dev_priv->wm.spr_latency[0] &&
6093 dev_priv->wm.cur_latency[0]) {
6094 dev_priv->display.update_wm = haswell_update_wm;
6095 dev_priv->display.update_sprite_wm =
6096 haswell_update_sprite_wm;
6098 DRM_DEBUG_KMS("Failed to read display plane latency. "
6100 dev_priv->display.update_wm = NULL;
6102 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6103 } else if (INTEL_INFO(dev)->gen == 8) {
6104 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6106 dev_priv->display.update_wm = NULL;
6107 } else if (IS_VALLEYVIEW(dev)) {
6108 dev_priv->display.update_wm = valleyview_update_wm;
6109 dev_priv->display.init_clock_gating =
6110 valleyview_init_clock_gating;
6111 } else if (IS_PINEVIEW(dev)) {
6112 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6115 dev_priv->mem_freq)) {
6116 DRM_INFO("failed to find known CxSR latency "
6117 "(found ddr%s fsb freq %d, mem freq %d), "
6119 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6120 dev_priv->fsb_freq, dev_priv->mem_freq);
6121 /* Disable CxSR and never update its watermark again */
6122 pineview_disable_cxsr(dev);
6123 dev_priv->display.update_wm = NULL;
6125 dev_priv->display.update_wm = pineview_update_wm;
6126 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6127 } else if (IS_G4X(dev)) {
6128 dev_priv->display.update_wm = g4x_update_wm;
6129 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6130 } else if (IS_GEN4(dev)) {
6131 dev_priv->display.update_wm = i965_update_wm;
6132 if (IS_CRESTLINE(dev))
6133 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6134 else if (IS_BROADWATER(dev))
6135 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6136 } else if (IS_GEN3(dev)) {
6137 dev_priv->display.update_wm = i9xx_update_wm;
6138 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6139 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6140 } else if (IS_I865G(dev)) {
6141 dev_priv->display.update_wm = i830_update_wm;
6142 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6143 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6144 } else if (IS_I85X(dev)) {
6145 dev_priv->display.update_wm = i9xx_update_wm;
6146 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6147 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6149 dev_priv->display.update_wm = i830_update_wm;
6150 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6152 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6154 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6158 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6160 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6162 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6163 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6167 I915_WRITE(GEN6_PCODE_DATA, *val);
6168 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6170 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6172 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6176 *val = I915_READ(GEN6_PCODE_DATA);
6177 I915_WRITE(GEN6_PCODE_DATA, 0);
6182 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6184 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6186 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6187 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6191 I915_WRITE(GEN6_PCODE_DATA, val);
6192 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6194 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6196 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6200 I915_WRITE(GEN6_PCODE_DATA, 0);
6205 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6210 switch (dev_priv->mem_freq) {
6224 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6227 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6232 switch (dev_priv->mem_freq) {
6246 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6249 void intel_pm_setup(struct drm_device *dev)
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6253 mutex_init(&dev_priv->rps.hw_lock);
6255 mutex_init(&dev_priv->pc8.lock);
6256 dev_priv->pc8.requirements_met = false;
6257 dev_priv->pc8.gpu_idle = false;
6258 dev_priv->pc8.irqs_disabled = false;
6259 dev_priv->pc8.enabled = false;
6260 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
6261 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
6262 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6263 intel_gen6_powersave_work);