/*
 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/arm/qcom-ids.h>

/ {
	model = "Qualcomm Technologies, Inc. MSM8916";
	compatible = "qcom,msm8916";
	qcom,msm-id =	<QCOM_ID_MSM8916 0>,
			<QCOM_ID_MSM8216 0>,
			<QCOM_ID_MSM8116 0>,
			<QCOM_ID_MSM8616 0>,
			<QCOM_ID_APQ8016 0>;


	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
	};

	chosen { };

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		reserve_aligned@86000000 {
			reg = <0x0 0x86000000 0x0 0x0300000>;
			no-map;
		};

		smem_mem: smem_region@86300000 {
			reg = <0x0 0x86300000 0x0 0x0100000>;
			no-map;
		};

                hypervisor_mem: hypervisor_region@86400000 {
                        no-map;
                        reg = <0x0 0x86400000 0x0 0x0400000>;
                };

		modem_adsp_mem: modem_adsp_region@86800000 {
                        no-map;
			reg = <0x0 0x86800000 0x0 0x04800000>;
		};

		rmtfs@86700000 {
			reg = <0x0 0x86700000 0x0 0xe0000>;
			no-map;
		};

                peripheral_mem: peripheral_region@8b600000 {
                        no-map;
                        reg = <0x0 0x8b600000 0x0 0x0600000>;
                };

		wcnss_mem: wcnss@89300000 {
			reg = <0x0 0x89300000 0x0 0x600000>;
			no-map;
		};

		vidc_mem: vidc_region@8f800000 {
			no-map;
			reg = <0 0x8f800000 0 0x800000>;
		};

		mba_mem: mba@8ea00000 {
			no-map;
			reg = <0 0x8ea00000 0 0x100000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc0>;
			next-level-cache = <&L2_0>;
			clocks = <&a53cc 1>;
			clock-latency = <200000>;
			cpu-supply = <&pm8916_spmi_s2>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      power-domain = <&l2ccc_0>;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x1>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc1>;
			next-level-cache = <&L2_0>;
			clocks = <&a53cc 1>;
			clock-latency = <200000>;
			cpu-supply = <&pm8916_spmi_s2>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x2>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc2>;
			next-level-cache = <&L2_0>;
			clocks = <&a53cc 1>;
			clock-latency = <200000>;
			cpu-supply = <&pm8916_spmi_s2>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x3>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc3>;
			next-level-cache = <&L2_0>;
			clocks = <&a53cc 1>;
			clock-latency = <200000>;
			cpu-supply = <&pm8916_spmi_s2>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};
	};

	cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
	};

	thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 4>;

			trips {
				cpu_alert0: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip@1 {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 3>;

			trips {
				cpu_alert1: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip@1 {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert1>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	firmware {
		compatible = "simple-bus";

		scm: scm {
			compatible = "qcom,scm";
			clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "core", "bus", "iface";
			#reset-cells = <1>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x4>;
		};

		msmgpio: pinctrl@1000000 {
			compatible = "qcom,msm8916-pinctrl";
			reg = <0x1000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gcc: qcom,gcc@1800000 {
			compatible = "qcom,gcc-msm8916";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x1800000 0x80000>;
		};

		tcsr_mutex_regs: syscon@1905000 {
			compatible = "syscon";
			reg = <0x1905000 0x20000>;
		};

		tcsr_mutex: hwlock {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_regs 0 0x1000>;
			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x60000 0x8000>;
		};

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		apcs: syscon@b011000 {
			compatible = "syscon";
			reg = <0x0b011000 0x1000>;
		};

		a53cc: qcom,a53cc@0b016000 {
			compatible = "qcom,clock-a53-msm8916";
			reg = <0x0b016000 0x40>;
			#clock-cells = <1>;
			qcom,apcs = <&apcs>;
		};

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp_spi1: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_default>;
			pinctrl-1 = <&spi1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi2: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_default>;
			pinctrl-1 = <&spi2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi3: spi@78b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi3_default>;
			pinctrl-1 = <&spi3_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi4: spi@78b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b8000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi4_default>;
			pinctrl-1 = <&spi4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi5: spi@78b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b9000 0x600>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 13>, <&blsp_dma 12>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi5_default>;
			pinctrl-1 = <&spi5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi6: spi@78ba000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078ba000 0x600>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi6_default>;
			pinctrl-1 = <&spi6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c2: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b6000 0x1000>;
			interrupts = <GIC_SPI 96 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c2_default>;
			pinctrl-1 = <&i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c4: i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b8000 0x1000>;
			interrupts = <GIC_SPI 98 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c4_default>;
			pinctrl-1 = <&i2c4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c6: i2c@78ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78ba000 0x1000>;
			interrupts = <GIC_SPI 100 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c6_default>;
			pinctrl-1 = <&i2c6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sdhc_1: sdhci@07824000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			bus-width = <8>;
			non-removable;
			status = "disabled";
		};

		sdhc_2: sdhci@07864000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
				 <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			bus-width = <4>;
			status = "disabled";
		};

		usb_dev: usb@78d9000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x78d9000 0x400>;
			dr_mode = "peripheral";
			interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
			usb-phy = <&usb_otg>;
			status = "disabled";
		};

		usb_host: ehci@78d9000 {
			compatible = "qcom,ehci-host";
			reg = <0x78d9000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
			usb-phy = <&usb_otg>;
			status = "disabled";
		};

		usb_otg: phy@78d9000 {
			compatible = "qcom,usb-otg-snps";
			reg = <0x78d9000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;

			v1p8-supply = <&pm8916_l7>;
			v3p3-supply = <&pm8916_l13>;
			qcom,vdd-levels = <1 5 7>;
			qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
			dr_mode = "peripheral";
			qcom,otg-control = <2>; // PMIC
			qcom,manual-pullup;

			qcom,msm-bus,name = "usb2";
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
					<87 512 0 0>,
					<87 512 80000 0>,
					<87 512 6000  6000>;

			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>,
				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
			clock-names = "iface", "core", "sleep";

			resets = <&gcc GCC_USB2A_PHY_BCR>,
				 <&gcc GCC_USB_HS_BCR>;
			reset-names = "phy", "link";
			status = "disabled";
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
		};

		l2ccc_0: clock-controller@b011000 {
			compatible = "qcom,8916-l2ccc";
			reg = <0x0b011000 0x1000>;
		};

		timer@b020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xb020000 0x1000>;
			clock-frequency = <19200000>;

			frame@b021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb021000 0x1000>,
				      <0xb022000 0x1000>;
			};

			frame@b023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb023000 0x1000>;
				status = "disabled";
			};

			frame@b024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb024000 0x1000>;
				status = "disabled";
			};

			frame@b025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb025000 0x1000>;
				status = "disabled";
			};

			frame@b026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb026000 0x1000>;
				status = "disabled";
			};

			frame@b027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb027000 0x1000>;
				status = "disabled";
			};

			frame@b028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb028000 0x1000>;
				status = "disabled";
			};
		};

		spmi_bus: spmi@200f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x200f000 0x001000>,
			      <0x2400000 0x400000>,
			      <0x2c00000 0x400000>,
			      <0x3800000 0x200000>,
			      <0x200a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		rng@22000 {
			compatible = "qcom,prng";
			reg = <0x00022000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};
		acc0: clock-controller@b088000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b088000 0x1000>,
			      <0x0b008000 0x1000>;
		};

		acc1: clock-controller@b098000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b098000 0x1000>,
			      <0x0b008000 0x1000>;
		};

		acc2: clock-controller@b0a8000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b0a8000 0x1000>,
			      <0x0b008000 0x1000>;
		};

		acc3: clock-controller@b0b8000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b0b8000 0x1000>,
			      <0x0b008000 0x1000>;
		};

		/* Audio */

		lpass_codec_core: lpass-codec{
			compatible = "syscon", "qcom,msm8916-lpass-codec";
			reg = <0x0771c000 0x400>;
		};

		lpass: lpass-cpu@07700000 {
			status = "disabled";
			compatible = "qcom,lpass-cpu-apq8016";
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;

			clock-names = "ahbix-clk",
					"pcnoc-mport-clk",
					"pcnoc-sway-clk",
					"mi2s-bit-clk0",
					"mi2s-bit-clk1",
					"mi2s-bit-clk2",
					"mi2s-bit-clk3";
			#sound-dai-cells = <1>;

			interrupts = <0 160 0>;
			interrupt-names = "lpass-irq-lpaif";
			reg = <0x07708000 0x10000>, <0x07702000 0x4>, <0x07702004 0x4>;
			reg-names = "lpass-lpaif", "mic-iomux", "spkr-iomux";
		};

		sound: sound {
			status = "disabled";
			compatible = "qcom,apq8016-sbc-sndcard";
			reg = <0x07702000 0x4>, <0x07702004 0x4>;
			reg-names = "mic-iomux", "spkr-iomux";
		};

	        tcsr: syscon@1937000 {
			compatible = "qcom,tcsr-msm8916", "syscon";
			reg = <0x1937000 0x30000>;
		};

		uqfprom: eeprom@58000 {
			compatible = "qcom,qfprom-msm8916";
			reg = <0x58000 0x7000>;
		};

		cpr@b018000 {
			compatible = "qcom,cpr";
			reg = <0xb018000 0x1000>;
			interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
			vdd-mx-supply = <&pm8916_l3>;
			acc-syscon = <&tcsr>;
			eeprom = <&uqfprom>;

			qcom,cpr-ref-clk = <19200>;
			qcom,cpr-timer-delay-us = <5000>;
			qcom,cpr-timer-cons-up = <0>;
			qcom,cpr-timer-cons-down = <2>;
			qcom,cpr-up-threshold = <0>;
			qcom,cpr-down-threshold = <2>;
			qcom,cpr-idle-clocks = <15>;
			qcom,cpr-gcnt-us = <1>;
			qcom,vdd-apc-step-up-limit = <1>;
			qcom,vdd-apc-step-down-limit = <1>;
			qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
		};

		qfprom: qfprom@5c000 {
			compatible = "qcom,qfprom";
			reg = <0x5c000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			tsens_caldata: caldata@d0 {
				reg = <0xd0 0x8>;
			};
			tsens_calsel: calsel@ec {
				reg = <0xec 0x4>;
			};
		};

		tsens: thermal-sensor@4a8000 {
			compatible = "qcom,msm8916-tsens";
			reg = <0x4a8000 0x2000>;
			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
			nvmem-cell-names = "calib", "calib_sel";
			qcom,tsens-slopes = <3200 3200 3200 3200 3200>;
			qcom,sensor-id = <0 1 2 4 5>;
			#thermal-sensor-cells = <1>;
		};

		hexagon@4080000 {
			compatible = "qcom,pil-q6v56-mss", "qcom,q6v5-pil";
			reg = <0x04080000 0x100>,
			      <0x04020000 0x040>;

			reg-names = "qdsp6", "rmb";

			interrupts-extended = <&intc 0 24 1>,
					      <&hexagon_smp2p_in 0 0>,
					      <&hexagon_smp2p_in 1 0>,
					      <&hexagon_smp2p_in 2 0>,
					      <&hexagon_smp2p_in 3 0>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>;
			clock-names = "iface", "bus", "mem";

			qcom,state = <&hexagon_smp2p_out 0>;
			qcom,state-names = "stop";

			resets = <&scm 0>;
			reset-names = "mss_restart";

			mx-supply = <&pm8916_l3>;
			pll-supply = <&pm8916_l7>;

			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;

			mba {
				memory-region = <&mba_mem>;
			};

			mpss {
				memory-region = <&modem_adsp_mem>;
			};
		};

		pronto: wcnss@a21b000 {
			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
			reg-names = "ccu", "dxe", "pmu";

			memory-region = <&wcnss_mem>;

			interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
				<&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
				<&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
				<&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
				<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

			vddmx-supply = <&pm8916_l3>;
			vddpx-supply = <&pm8916_l7>;

			qcom,state = <&wcnss_smp2p_out 0>;
			qcom,state-names = "stop";

			pinctrl-names = "default";
			pinctrl-0 = <&wcnss_default>;

			iris {
				compatible = "qcom,wcn3620";

				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
				clock-names = "xo";

				vddxo-supply = <&pm8916_l7>;
				vddrfa-supply = <&pm8916_s3>;
				vddpa-supply = <&pm8916_l9>;
				vdddig-supply = <&pm8916_l5>;
			};
		};

		qcom,rpm-log@29dc00 {
			compatible = "qcom,rpm-log";
			reg = <0x29dc00 0x4000>;
			qcom,rpm-addr-phys = <0x200000>;
			qcom,offset-version = <4>;
			qcom,offset-page-buffer-addr = <36>;
			qcom,offset-log-len = <40>;
			qcom,offset-log-len-mask = <44>;
			qcom,offset-page-indices = <56>;
		};

		vidc_rproc: vidc_tzpil@0 {
			compatible = "qcom,tz-pil";
			clocks = <&gcc GCC_CRYPTO_CLK>,
				 <&gcc GCC_CRYPTO_AHB_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc CRYPTO_CLK_SRC>;
			clock-names = "scm_core_clk", "scm_iface_clk",
				      "scm_bus_clk", "scm_src_clk";
			qcom,firmware-name = "venus";
			qcom,pas-id = <9>;
			memory-region = <&vidc_mem>;
			status = "disabled";
		};

		vidc: qcom,vidc@1d00000 {
			compatible = "qcom,msm-vidc";
			reg = <0x01d00000 0xff000>;
			interrupts = <GIC_SPI 44 0>;
			power-domains = <&gcc VENUS_GDSC>;
			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
				 <&gcc GCC_VENUS0_AHB_CLK>,
				 <&gcc GCC_VENUS0_AXI_CLK>;
			clock-names = "core_clk", "iface_clk", "bus_clk";
			qcom,hfi = "venus";
			qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
			qcom,enable-idle-indicator;
			rproc = <&vidc_rproc>;
			qcom,iommu-cb = <&venus_ns>,
					<&venus_sec_bitstream>,
					<&venus_sec_pixel>,
					<&venus_sec_non_pixel>;
			status = "disabled";
		};
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_mem>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};
	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;
			qcom,remote-pid = <0xffffffff>;

			rpm_requests {
				compatible = "qcom,rpm-msm8916";
				qcom,smd-channels = "rpm_requests";
				rpmcc: qcom,rpmcc {
					compatible = "qcom,rpmcc-msm8916";
					#clock-cells = <1>;
				};

				msm-bus {
						compatible = "qcom,rpm-msm-bus";
				};
				pm8916-regulators {
					compatible = "qcom,rpm-pm8916-regulators";

					pm8916_s1: s1 {};
					pm8916_s2: s2 {};
					pm8916_s3: s3 {};
					pm8916_s4: s4 {};

					pm8916_l1: l1 {};
					pm8916_l2: l2 {};
					pm8916_l3: l3 {};
					pm8916_l4: l4 {};
					pm8916_l5: l5 {};
					pm8916_l6: l6 {};
					pm8916_l7: l7 {};
					pm8916_l8: l8 {};
					pm8916_l9: l9 {};
					pm8916_l10: l10 {};
					pm8916_l11: l11 {};
					pm8916_l12: l12 {};
					pm8916_l13: l13 {};
					pm8916_l14: l14 {};
					pm8916_l15: l15 {};
					pm8916_l16: l16 {};
					pm8916_l17: l17 {};
					pm8916_l18: l18 {};
				};
			};
		};

		qcom,smd-modem {
			interrupts = <0 25 1>;
			qcom,smd-edge = <0>;
			qcom,ipc = <&apcs 8 12>;
			qcom,remote-pid = <1>;
			ipcrtr_requests {
				compatible = "qcom,ipcrtr";
				qcom,smd-channels = "IPCRTR";
			};
		};

		pronto {
			interrupts = <0 142 1>;

			qcom,ipc = <&apcs 8 17>;
			qcom,smd-edge = <6>;
			qcom,remote-pid = <4>;

			wcnss {
				compatible = "qcom,wcnss";
				qcom,smd-channels = "WCNSS_CTRL";

				qcom,mmio = <&pronto>;

				bt {
					compatible = "qcom,wcnss-bt";
				};

				wifi {
					compatible = "qcom,wcnss-wlan";

					interrupts = <0 145 0>, <0 146 0>;
					interrupt-names = "tx", "rx";

					qcom,state = <&apps_smsm 10>, <&apps_smsm 9>;
					qcom,state-names = "tx-enable", "tx-rings-empty";
				};
			};
		};
	};

	hexagon-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 14>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		hexagon_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			#qcom,state-cells = <1>;
		};

		hexagon_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	wcnss-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

		interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 18>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <4>;

		wcnss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			#qcom,state-cells = <1>;
		};

		wcnss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smsm {
		compatible = "qcom,smsm";

		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ipc-1 = <&apcs 0 13>;
		qcom,ipc-6 = <&apcs 0 19>;

		apps_smsm: apps@0 {
			reg = <0>;

			#qcom,state-cells = <1>;
		};

		hexagon_smsm: hexagon@1 {
			reg = <1>;
			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wcnss_smsm: wcnss@6 {
			reg = <6>;
			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};
};

#include "msm8916-pins.dtsi"
#include "msm8916-iommu.dtsi"
#include "msm8916-coresight.dtsi"
#include "msm8916-bus.dtsi"