+ writel(CLK_24MHZ, &usb->usbphyclk);
+
+ clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+ PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+ PHYPWR_NORMAL_MASK_PHY0));
+
+ setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+ udelay(10);
+ clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+}
+
+static void setup_usb_phy(struct exynos_usb_phy *usb)
+{
+ set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
+
+ set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
+
+ if (cpu_is_exynos5())
+ exynos5_setup_usb_phy(usb);
+ else if (cpu_is_exynos4())
+ if (proid_is_exynos4412())
+ exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
+ usb);
+}
+
+static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
+{
+ u32 hsic_ctrl;
+