+
+#elif defined(CONFIG_MPC8309)
+/* SICR_1 */
+#define SICR_1_UART1_UART1S (0 << (30-2))
+#define SICR_1_UART1_UART1RTS (1 << (30-2))
+#define SICR_1_I2C_I2C (0 << (30-4))
+#define SICR_1_I2C_CKSTOP (1 << (30-4))
+#define SICR_1_IRQ_A_IRQ (0 << (30-6))
+#define SICR_1_IRQ_A_MCP (1 << (30-6))
+#define SICR_1_IRQ_B_IRQ (0 << (30-8))
+#define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
+#define SICR_1_GPIO_A_GPIO (0 << (30-10))
+#define SICR_1_GPIO_A_SD (2 << (30-10))
+#define SICR_1_GPIO_A_DDR (3 << (30-10))
+#define SICR_1_GPIO_B_GPIO (0 << (30-12))
+#define SICR_1_GPIO_B_SD (2 << (30-12))
+#define SICR_1_GPIO_B_QE (3 << (30-12))
+#define SICR_1_GPIO_C_GPIO (0 << (30-14))
+#define SICR_1_GPIO_C_CAN (1 << (30-14))
+#define SICR_1_GPIO_C_DDR (2 << (30-14))
+#define SICR_1_GPIO_C_LCS (3 << (30-14))
+#define SICR_1_GPIO_D_GPIO (0 << (30-16))
+#define SICR_1_GPIO_D_CAN (1 << (30-16))
+#define SICR_1_GPIO_D_DDR (2 << (30-16))
+#define SICR_1_GPIO_D_LCS (3 << (30-16))
+#define SICR_1_GPIO_E_GPIO (0 << (30-18))
+#define SICR_1_GPIO_E_CAN (1 << (30-18))
+#define SICR_1_GPIO_E_DDR (2 << (30-18))
+#define SICR_1_GPIO_E_LCS (3 << (30-18))
+#define SICR_1_GPIO_F_GPIO (0 << (30-20))
+#define SICR_1_GPIO_F_CAN (1 << (30-20))
+#define SICR_1_GPIO_F_CK (2 << (30-20))
+#define SICR_1_USB_A_USBDR (0 << (30-22))
+#define SICR_1_USB_A_UART2S (1 << (30-22))
+#define SICR_1_USB_B_USBDR (0 << (30-24))
+#define SICR_1_USB_B_UART2S (1 << (30-24))
+#define SICR_1_USB_B_UART2RTS (2 << (30-24))
+#define SICR_1_USB_C_USBDR (0 << (30-26))
+#define SICR_1_USB_C_QE_EXT (3 << (30-26))
+#define SICR_1_FEC1_FEC1 (0 << (30-28))
+#define SICR_1_FEC1_GTM (1 << (30-28))
+#define SICR_1_FEC1_GPIO (2 << (30-28))
+#define SICR_1_FEC2_FEC2 (0 << (30-30))
+#define SICR_1_FEC2_GTM (1 << (30-30))
+#define SICR_1_FEC2_GPIO (2 << (30-30))
+/* SICR_2 */
+#define SICR_2_FEC3_FEC3 (0 << (30-0))
+#define SICR_2_FEC3_TMR (1 << (30-0))
+#define SICR_2_FEC3_GPIO (2 << (30-0))
+#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
+#define SICR_2_HDLC1_A_GPIO (1 << (30-2))
+#define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
+#define SICR_2_ELBC_A_LA (0 << (30-4))
+#define SICR_2_ELBC_B_LCLK (0 << (30-6))
+#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
+#define SICR_2_HDLC2_A_GPIO (0 << (30-8))
+#define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
+/* bits 10-11 unused */
+#define SICR_2_USB_D_USBDR (0 << (30-12))
+#define SICR_2_USB_D_GPIO (2 << (30-12))
+#define SICR_2_USB_D_QE_BRG (3 << (30-12))
+#define SICR_2_PCI_PCI (0 << (30-14))
+#define SICR_2_PCI_CPCI_HS (2 << (30-14))
+#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
+#define SICR_2_HDLC1_B_GPIO (1 << (30-16))
+#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
+#define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
+#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
+#define SICR_2_HDLC1_C_GPIO (1 << (30-18))
+#define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
+#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
+#define SICR_2_HDLC2_B_GPIO (1 << (30-20))
+#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
+#define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
+#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
+#define SICR_2_HDLC2_C_GPIO (1 << (30-22))
+#define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
+#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
+#define SICR_2_QUIESCE_B (0 << (30-24))
+