-#define MAMR_PTB_MSK 0xff000000 /* Periodic Timer B period mask */
-#define MAMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */
-#define MAMR_PTBE 0x00800000 /* Periodic Timer B Enable */
-#define MAMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */
-#define MAMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
-#define MAMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
-#define MAMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
-#define MAMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
-#define MAMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
-#define MAMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
-#define MAMR_DSB_MSK 0x00060000 /* Disable Timer period mask */
-#define MAMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */
-#define MAMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */
-#define MAMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */
-#define MAMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */
-#define MAMR_G0CLB_MSK 0x0000e000 /* General Line 0 Control B */
-#define MAMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */
-#define MAMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */
-#define MAMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */
-#define MAMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */
-#define MAMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */
-#define MAMR_G0CLB_A7 0x0000a000 /* General Line 0 : A7 */
-#define MAMR_G0CLB_A6 0x0000b000 /* General Line 0 : A6 */
-#define MAMR_G0CLB_A5 0x0000e000 /* General Line 0 : A5 */
-#define MAMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */
-#define MAMR_RLFB_MSK 0x00000f00 /* Read Loop Field B mask */
-#define MAMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */
-#define MAMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */
-#define MAMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */
-#define MAMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */
-#define MAMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */
-#define MAMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */
-#define MAMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */
-#define MAMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */
-#define MAMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */
-#define MAMR_RLFB_10X 0x00000a00 /* The Read Loop is executed 10 times */
-#define MAMR_RLFB_11X 0x00000b00 /* The Read Loop is executed 11 times */
-#define MAMR_RLFB_12X 0x00000c00 /* The Read Loop is executed 12 times */
-#define MAMR_RLFB_13X 0x00000d00 /* The Read Loop is executed 13 times */
-#define MAMR_RLFB_14X 0x00000e00 /* The Read Loop is executed 14 times */
-#define MAMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */
-#define MAMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */
-#define MAMR_WLFB_MSK 0x000000f0 /* Write Loop Field B mask */
-#define MAMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */
-#define MAMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */
-#define MAMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */
-#define MAMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */
-#define MAMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */
-#define MAMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */
-#define MAMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */
-#define MAMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */
-#define MAMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */
-#define MAMR_WLFB_10X 0x000000a0 /* The Write Loop is executed 10 times */
-#define MAMR_WLFB_11X 0x000000b0 /* The Write Loop is executed 11 times */
-#define MAMR_WLFB_12X 0x000000c0 /* The Write Loop is executed 12 times */
-#define MAMR_WLFB_13X 0x000000d0 /* The Write Loop is executed 13 times */
-#define MAMR_WLFB_14X 0x000000e0 /* The Write Loop is executed 14 times */
-#define MAMR_WLFB_15X 0x000000f0 /* The Write Loop is executed 15 times */
-#define MAMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */
-#define MAMR_TLFB_MSK 0x0000000f /* Timer Loop Field B mask */
-#define MAMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */
-#define MAMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */
-#define MAMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */
-#define MAMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */
-#define MAMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */
-#define MAMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */
-#define MAMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */
-#define MAMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */
-#define MAMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */
-#define MAMR_TLFB_10X 0x0000000a /* The Timer Loop is executed 10 times */
-#define MAMR_TLFB_11X 0x0000000b /* The Timer Loop is executed 11 times */
-#define MAMR_TLFB_12X 0x0000000c /* The Timer Loop is executed 12 times */
-#define MAMR_TLFB_13X 0x0000000d /* The Timer Loop is executed 13 times */
-#define MAMR_TLFB_14X 0x0000000e /* The Timer Loop is executed 14 times */
-#define MAMR_TLFB_15X 0x0000000f /* The Timer Loop is executed 15 times */
-#define MAMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */
+#define MBMR_PTB_MSK 0xFF000000 /* Periodic Timer B period mask */
+#define MBMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */
+#define MBMR_PTBE 0x00800000 /* Periodic Timer B Enable */
+#define MBMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */
+#define MBMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
+#define MBMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
+#define MBMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
+#define MBMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
+#define MBMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
+#define MBMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
+#define MBMR_DSB_MSK 0x00060000 /* Disable Timer period mask */
+#define MBMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */
+#define MBMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */
+#define MBMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */
+#define MBMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */
+#define MBMR_G0CLB_MSK 0x0000E000 /* General Line 0 Control B */
+#define MBMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */
+#define MBMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */
+#define MBMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */
+#define MBMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */
+#define MBMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */
+#define MBMR_G0CLB_A7 0x0000A000 /* General Line 0 : A7 */
+#define MBMR_G0CLB_A6 0x0000C000 /* General Line 0 : A6 */
+#define MBMR_G0CLB_A5 0x0000E000 /* General Line 0 : A5 */
+#define MBMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */
+#define MBMR_RLFB_MSK 0x00000F00 /* Read Loop Field B mask */
+#define MBMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */
+#define MBMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */
+#define MBMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */
+#define MBMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */
+#define MBMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */
+#define MBMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */
+#define MBMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */
+#define MBMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */
+#define MBMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */
+#define MBMR_RLFB_10X 0x00000A00 /* The Read Loop is executed 10 times */
+#define MBMR_RLFB_11X 0x00000B00 /* The Read Loop is executed 11 times */
+#define MBMR_RLFB_12X 0x00000C00 /* The Read Loop is executed 12 times */
+#define MBMR_RLFB_13X 0x00000D00 /* The Read Loop is executed 13 times */
+#define MBMR_RLFB_14X 0x00000E00 /* The Read Loop is executed 14 times */
+#define MBMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */
+#define MBMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */
+#define MBMR_WLFB_MSK 0x000000F0 /* Write Loop Field B mask */
+#define MBMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */
+#define MBMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */
+#define MBMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */
+#define MBMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */
+#define MBMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */
+#define MBMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */
+#define MBMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */
+#define MBMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */
+#define MBMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */
+#define MBMR_WLFB_10X 0x000000A0 /* The Write Loop is executed 10 times */
+#define MBMR_WLFB_11X 0x000000B0 /* The Write Loop is executed 11 times */
+#define MBMR_WLFB_12X 0x000000C0 /* The Write Loop is executed 12 times */
+#define MBMR_WLFB_13X 0x000000D0 /* The Write Loop is executed 13 times */
+#define MBMR_WLFB_14X 0x000000E0 /* The Write Loop is executed 14 times */
+#define MBMR_WLFB_15X 0x000000F0 /* The Write Loop is executed 15 times */
+#define MBMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */
+#define MBMR_TLFB_MSK 0x0000000F /* Timer Loop Field B mask */
+#define MBMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */
+#define MBMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */
+#define MBMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */
+#define MBMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */
+#define MBMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */
+#define MBMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */
+#define MBMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */
+#define MBMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */
+#define MBMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */
+#define MBMR_TLFB_10X 0x0000000A /* The Timer Loop is executed 10 times */
+#define MBMR_TLFB_11X 0x0000000B /* The Timer Loop is executed 11 times */
+#define MBMR_TLFB_12X 0x0000000C /* The Timer Loop is executed 12 times */
+#define MBMR_TLFB_13X 0x0000000D /* The Timer Loop is executed 13 times */
+#define MBMR_TLFB_14X 0x0000000E /* The Timer Loop is executed 14 times */
+#define MBMR_TLFB_15X 0x0000000F /* The Timer Loop is executed 15 times */
+#define MBMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */
-#define TMR_PS_MSK 0xff00 /* Prescaler Value */
-#define TMR_PS_SHIFT 8 /* Prescaler position */
-#define TMR_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt */
-#define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */
-#define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
-#define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
-#define TMR_CE_ANY 0x00c0 /* Capture on any TINx edge */
-#define TMR_OM 0x0020 /* Output Mode */
-#define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */
-#define TMR_FRR 0x0008 /* Free Run/Restart */
-#define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
-#define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
-#define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */
-#define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */
-#define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */
-#define TMR_GE 0x0001 /* Gate Enable */
+#define TMR_PS_MSK 0xFF00 /* Prescaler Value */
+#define TMR_PS_SHIFT 8 /* Prescaler position */
+#define TMR_CE_MSK 0x00C0 /* Capture Edge and Enable Interrupt */
+#define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */
+#define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
+#define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
+#define TMR_CE_ANY 0x00C0 /* Capture on any TINx edge */
+#define TMR_OM 0x0020 /* Output Mode */
+#define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */
+#define TMR_FRR 0x0008 /* Free Run/Restart */
+#define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
+#define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
+#define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */
+#define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */
+#define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */
+#define TMR_GE 0x0001 /* Gate Enable */