-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
-
-// CRTC_GEN_CNTL
-#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
-#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
-#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
-#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
-#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
-#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
-#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
-#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
-#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
-#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
-#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
-#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
-#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
-#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
-#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
-#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
-#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
-#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
-#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
-
-// CRTC2_GEN_CNTL
-#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
-#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
-#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
-#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
-#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
-#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
-#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
-#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
-#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
-#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
-#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
-#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
-#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
-#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
-#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
-#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
-#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
-#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
-#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
-
-// AGP_CNTL
-#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
-#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
-#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
-#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
-#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
-#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
-#define AGP_CNTL__EN_2X_STBB 0x00000400L
-#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
-#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
-#define AGP_CNTL__SBA_DIS_MASK 0x00001000L
-#define AGP_CNTL__SBA_DIS 0x00001000L
-#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
-#define AGP_CNTL__AGP_REV_ID 0x00002000L
-#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
-#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
-#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
-#define AGP_CNTL__FORCE_INT_VREF 0x00010000L
-#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
-#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
-#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
-#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
-#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
-#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
-#define AGP_CNTL__EN_RBFCALM 0x00800000L
-#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
-#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
-#define AGP_CNTL__DIS_RBF_MASK 0x02000000L
-#define AGP_CNTL__DIS_RBF 0x02000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
-#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
-
-// AGP_CNTL
-#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
-#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
-#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
-#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
-#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
-#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
-#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
-#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
-#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
-#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
-#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
-#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
-#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
-#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
-#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
-#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
-#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
-#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
-
-// DISP_MISC_CNTL
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
-#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
-#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
-#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
-#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
-#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
-#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
-#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
-#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
-#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
-#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
-#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
-#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
-#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
-#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
-
-// DISP_PWR_MAN
-#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
-#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
-#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
-#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
-#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
-#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
-#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
-#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
-#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
-#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
-#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
-#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
-#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
-#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
-#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
-#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
-#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
-#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
-#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
-#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
-#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
-#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
-#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
-#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
-#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
-#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
-#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
-
-// MC_IND_INDEX
-#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
-#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
-#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
-
-// MC_IND_DATA
-#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
-
-// MC_CHP_IO_CNTL_A1
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
-#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
-#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
-#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
-
-// MC_CHP_IO_CNTL_B1
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
-#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
-#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
-#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
-
-// MC_CHP_IO_CNTL_A1
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
-#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
-
-// MC_CHP_IO_CNTL_B1
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
-#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
-
-// MEM_SDRAM_MODE_REG
-#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
-#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
-#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
-
-// MEM_SDRAM_MODE_REG
-#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
-#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
-#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
-
-// MEM_REFRESH_CNTL
-#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
-#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
-#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
-#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
-#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
-#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
-#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
-#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
-#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
-#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
-#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
-#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
-
-// MC_STATUS
-#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
-#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
-#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
-#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
-#define MC_STATUS__MC_IDLE_MASK 0x00000004L
-#define MC_STATUS__MC_IDLE 0x00000004L
-#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
-#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
-#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
-#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
-#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
-#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
-#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
-#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
-#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
-#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
-
-// MDLL_CKO
-#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
-#define MDLL_CKO__MCKOA_SLEEP 0x00000001L
-#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
-#define MDLL_CKO__MCKOA_RESET 0x00000002L
-#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
-#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
-#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
-#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
-#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
-#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
-#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
-#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
-#define MDLL_CKO__MCKOB_SLEEP 0x00010000L
-#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
-#define MDLL_CKO__MCKOB_RESET 0x00020000L
-#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
-#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
-#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
-#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
-#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
-#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
-#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
-
-// MDLL_RDCKA
-#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
-#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
-#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
-#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
-#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
-#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
-#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
-#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
-#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
-#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
-#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
-#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
-#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
-#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
-#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
-#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
-#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
-#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
-#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
-#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
-#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
-#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
-#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
-#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
-#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
-#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
-
-// MDLL_RDCKB
-#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
-#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
-#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
-#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
-#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
-#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
-#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
-#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
-#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
-#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
-#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
-#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
-#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
-#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
-#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
-#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
-#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
-#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
-#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
-#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
-#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
-#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
-#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
-#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
-#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
-#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
-
-#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
-#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
-#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
-#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
-#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
-#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
-#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
-#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
-
-#define pllCLK_PIN_CNTL 0x0001
-#define pllPPLL_CNTL 0x0002
-#define pllPPLL_REF_DIV 0x0003
-#define pllPPLL_DIV_0 0x0004
-#define pllPPLL_DIV_1 0x0005
-#define pllPPLL_DIV_2 0x0006
-#define pllPPLL_DIV_3 0x0007
-#define pllVCLK_ECP_CNTL 0x0008
-#define pllHTOTAL_CNTL 0x0009
-#define pllM_SPLL_REF_FB_DIV 0x000A
-#define pllAGP_PLL_CNTL 0x000B
-#define pllSPLL_CNTL 0x000C
-#define pllSCLK_CNTL 0x000D
-#define pllMPLL_CNTL 0x000E
-#define pllMDLL_CKO 0x000F
-#define pllMDLL_RDCKA 0x0010
-#define pllMDLL_RDCKB 0x0011
-#define pllMCLK_CNTL 0x0012
-#define pllPLL_TEST_CNTL 0x0013
-#define pllCLK_PWRMGT_CNTL 0x0014
-#define pllPLL_PWRMGT_CNTL 0x0015
-#define pllCG_TEST_MACRO_RW_WRITE 0x0016
-#define pllCG_TEST_MACRO_RW_READ 0x0017
-#define pllCG_TEST_MACRO_RW_DATA 0x0018
-#define pllCG_TEST_MACRO_RW_CNTL 0x0019
-#define pllDISP_TEST_MACRO_RW_WRITE 0x001A
-#define pllDISP_TEST_MACRO_RW_READ 0x001B
-#define pllDISP_TEST_MACRO_RW_DATA 0x001C
-#define pllDISP_TEST_MACRO_RW_CNTL 0x001D
-#define pllSCLK_CNTL2 0x001E
-#define pllMCLK_MISC 0x001F
-#define pllTV_PLL_FINE_CNTL 0x0020
-#define pllTV_PLL_CNTL 0x0021
-#define pllTV_PLL_CNTL1 0x0022
-#define pllTV_DTO_INCREMENTS 0x0023
-#define pllSPLL_AUX_CNTL 0x0024
-#define pllMPLL_AUX_CNTL 0x0025
-#define pllP2PLL_CNTL 0x002A
-#define pllP2PLL_REF_DIV 0x002B
-#define pllP2PLL_DIV_0 0x002C
-#define pllPIXCLKS_CNTL 0x002D
-#define pllHTOTAL2_CNTL 0x002E
-#define pllSSPLL_CNTL 0x0030
-#define pllSSPLL_REF_DIV 0x0031
-#define pllSSPLL_DIV_0 0x0032
-#define pllSS_INT_CNTL 0x0033
-#define pllSS_TST_CNTL 0x0034
-#define pllSCLK_MORE_CNTL 0x0035
-
-#define ixMC_PERF_CNTL 0x0000
-#define ixMC_PERF_SEL 0x0001
-#define ixMC_PERF_REGION_0 0x0002
-#define ixMC_PERF_REGION_1 0x0003
-#define ixMC_PERF_COUNT_0 0x0004
-#define ixMC_PERF_COUNT_1 0x0005
-#define ixMC_PERF_COUNT_2 0x0006
-#define ixMC_PERF_COUNT_3 0x0007
-#define ixMC_PERF_COUNT_MEMCH_A 0x0008
-#define ixMC_PERF_COUNT_MEMCH_B 0x0009
-#define ixMC_IMP_CNTL 0x000A
-#define ixMC_CHP_IO_CNTL_A0 0x000B
-#define ixMC_CHP_IO_CNTL_A1 0x000C
-#define ixMC_CHP_IO_CNTL_B0 0x000D
-#define ixMC_CHP_IO_CNTL_B1 0x000E
-#define ixMC_IMP_CNTL_0 0x000F
-#define ixTC_MISMATCH_1 0x0010
-#define ixTC_MISMATCH_2 0x0011
-#define ixMC_BIST_CTRL 0x0012
-#define ixREG_COLLAR_WRITE 0x0013
-#define ixREG_COLLAR_READ 0x0014
-#define ixR300_MC_IMP_CNTL 0x0018
-#define ixR300_MC_CHP_IO_CNTL_A0 0x0019
-#define ixR300_MC_CHP_IO_CNTL_A1 0x001a
-#define ixR300_MC_CHP_IO_CNTL_B0 0x001b
-#define ixR300_MC_CHP_IO_CNTL_B1 0x001c
-#define ixR300_MC_CHP_IO_CNTL_C0 0x001d
-#define ixR300_MC_CHP_IO_CNTL_C1 0x001e
-#define ixR300_MC_CHP_IO_CNTL_D0 0x001f
-#define ixR300_MC_CHP_IO_CNTL_D1 0x0020
-#define ixR300_MC_IMP_CNTL_0 0x0021
-#define ixR300_MC_ELPIDA_CNTL 0x0022
-#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
-#define ixR300_MC_READ_CNTL_CD 0x0024
-#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
-#define ixR300_MC_DEBUG_CNTL 0x0026
-#define ixR300_MC_BIST_CNTL_0 0x0028
-#define ixR300_MC_BIST_CNTL_1 0x0029
-#define ixR300_MC_BIST_CNTL_2 0x002a
-#define ixR300_MC_BIST_CNTL_3 0x002b
-#define ixR300_MC_BIST_CNTL_4 0x002c
-#define ixR300_MC_BIST_CNTL_5 0x002d
-#define ixR300_MC_IMP_STATUS 0x002e
-#define ixR300_MC_DLL_CNTL 0x002f
-#define NB_TOM 0x15C
-
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
+
+/* CRTC_GEN_CNTL */
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
+#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
+#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
+#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
+#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
+
+/* CRTC2_GEN_CNTL */
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
+#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
+#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
+#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
+#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
+#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
+#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
+#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
+#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
+#define AGP_CNTL__EN_2X_STBB 0x00000400L
+#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
+#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
+#define AGP_CNTL__SBA_DIS_MASK 0x00001000L
+#define AGP_CNTL__SBA_DIS 0x00001000L
+#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
+#define AGP_CNTL__AGP_REV_ID 0x00002000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
+#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
+#define AGP_CNTL__FORCE_INT_VREF 0x00010000L
+#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
+#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
+#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
+#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
+#define AGP_CNTL__EN_RBFCALM 0x00800000L
+#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
+#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
+#define AGP_CNTL__DIS_RBF_MASK 0x02000000L
+#define AGP_CNTL__DIS_RBF 0x02000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
+#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
+#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
+#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
+#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
+#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
+#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
+#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
+#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
+#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
+#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
+#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
+#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
+#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
+#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
+#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
+#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
+
+/* DISP_MISC_CNTL */
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
+#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
+#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
+#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
+#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
+
+/* DISP_PWR_MAN */
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
+#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
+#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
+#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
+
+/* MC_IND_INDEX */
+#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
+#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
+#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
+
+/* MC_IND_DATA */
+#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
+
+/* MEM_REFRESH_CNTL */
+#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
+#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
+
+/* MC_STATUS */
+#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
+#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
+#define MC_STATUS__MC_IDLE_MASK 0x00000004L
+#define MC_STATUS__MC_IDLE 0x00000004L
+#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
+#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
+#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
+#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
+#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
+#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
+#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
+#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
+#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
+#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
+
+/* MDLL_CKO */
+#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
+#define MDLL_CKO__MCKOA_SLEEP 0x00000001L
+#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
+#define MDLL_CKO__MCKOA_RESET 0x00000002L
+#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
+#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
+#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
+#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
+#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
+#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
+#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
+#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
+#define MDLL_CKO__MCKOB_SLEEP 0x00010000L
+#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
+#define MDLL_CKO__MCKOB_RESET 0x00020000L
+#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
+#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
+#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
+#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
+#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
+#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
+#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
+
+/* MDLL_RDCKA */
+#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
+#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
+#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
+#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
+#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
+#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
+#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
+#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
+#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
+#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
+#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
+#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
+#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
+#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
+
+/* MDLL_RDCKB */
+#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
+#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
+#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
+#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
+#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
+#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
+#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
+#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
+#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
+#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
+#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
+#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
+#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
+#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
+
+#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
+#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
+#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
+#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
+#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
+#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
+#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
+#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
+
+#define pllCLK_PIN_CNTL 0x0001
+#define pllPPLL_CNTL 0x0002
+#define pllPPLL_REF_DIV 0x0003
+#define pllPPLL_DIV_0 0x0004
+#define pllPPLL_DIV_1 0x0005
+#define pllPPLL_DIV_2 0x0006
+#define pllPPLL_DIV_3 0x0007
+#define pllVCLK_ECP_CNTL 0x0008
+#define pllHTOTAL_CNTL 0x0009
+#define pllM_SPLL_REF_FB_DIV 0x000A
+#define pllAGP_PLL_CNTL 0x000B
+#define pllSPLL_CNTL 0x000C
+#define pllSCLK_CNTL 0x000D
+#define pllMPLL_CNTL 0x000E
+#define pllMDLL_CKO 0x000F
+#define pllMDLL_RDCKA 0x0010
+#define pllMDLL_RDCKB 0x0011
+#define pllMCLK_CNTL 0x0012
+#define pllPLL_TEST_CNTL 0x0013
+#define pllCLK_PWRMGT_CNTL 0x0014
+#define pllPLL_PWRMGT_CNTL 0x0015
+#define pllCG_TEST_MACRO_RW_WRITE 0x0016
+#define pllCG_TEST_MACRO_RW_READ 0x0017
+#define pllCG_TEST_MACRO_RW_DATA 0x0018
+#define pllCG_TEST_MACRO_RW_CNTL 0x0019
+#define pllDISP_TEST_MACRO_RW_WRITE 0x001A
+#define pllDISP_TEST_MACRO_RW_READ 0x001B
+#define pllDISP_TEST_MACRO_RW_DATA 0x001C
+#define pllDISP_TEST_MACRO_RW_CNTL 0x001D
+#define pllSCLK_CNTL2 0x001E
+#define pllMCLK_MISC 0x001F
+#define pllTV_PLL_FINE_CNTL 0x0020
+#define pllTV_PLL_CNTL 0x0021
+#define pllTV_PLL_CNTL1 0x0022
+#define pllTV_DTO_INCREMENTS 0x0023
+#define pllSPLL_AUX_CNTL 0x0024
+#define pllMPLL_AUX_CNTL 0x0025
+#define pllP2PLL_CNTL 0x002A
+#define pllP2PLL_REF_DIV 0x002B
+#define pllP2PLL_DIV_0 0x002C
+#define pllPIXCLKS_CNTL 0x002D
+#define pllHTOTAL2_CNTL 0x002E
+#define pllSSPLL_CNTL 0x0030
+#define pllSSPLL_REF_DIV 0x0031
+#define pllSSPLL_DIV_0 0x0032
+#define pllSS_INT_CNTL 0x0033
+#define pllSS_TST_CNTL 0x0034
+#define pllSCLK_MORE_CNTL 0x0035
+
+#define ixMC_PERF_CNTL 0x0000
+#define ixMC_PERF_SEL 0x0001
+#define ixMC_PERF_REGION_0 0x0002
+#define ixMC_PERF_REGION_1 0x0003
+#define ixMC_PERF_COUNT_0 0x0004
+#define ixMC_PERF_COUNT_1 0x0005
+#define ixMC_PERF_COUNT_2 0x0006
+#define ixMC_PERF_COUNT_3 0x0007
+#define ixMC_PERF_COUNT_MEMCH_A 0x0008
+#define ixMC_PERF_COUNT_MEMCH_B 0x0009
+#define ixMC_IMP_CNTL 0x000A
+#define ixMC_CHP_IO_CNTL_A0 0x000B
+#define ixMC_CHP_IO_CNTL_A1 0x000C
+#define ixMC_CHP_IO_CNTL_B0 0x000D
+#define ixMC_CHP_IO_CNTL_B1 0x000E
+#define ixMC_IMP_CNTL_0 0x000F
+#define ixTC_MISMATCH_1 0x0010
+#define ixTC_MISMATCH_2 0x0011
+#define ixMC_BIST_CTRL 0x0012
+#define ixREG_COLLAR_WRITE 0x0013
+#define ixREG_COLLAR_READ 0x0014
+#define ixR300_MC_IMP_CNTL 0x0018
+#define ixR300_MC_CHP_IO_CNTL_A0 0x0019
+#define ixR300_MC_CHP_IO_CNTL_A1 0x001a
+#define ixR300_MC_CHP_IO_CNTL_B0 0x001b
+#define ixR300_MC_CHP_IO_CNTL_B1 0x001c
+#define ixR300_MC_CHP_IO_CNTL_C0 0x001d
+#define ixR300_MC_CHP_IO_CNTL_C1 0x001e
+#define ixR300_MC_CHP_IO_CNTL_D0 0x001f
+#define ixR300_MC_CHP_IO_CNTL_D1 0x0020
+#define ixR300_MC_IMP_CNTL_0 0x0021
+#define ixR300_MC_ELPIDA_CNTL 0x0022
+#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
+#define ixR300_MC_READ_CNTL_CD 0x0024
+#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
+#define ixR300_MC_DEBUG_CNTL 0x0026
+#define ixR300_MC_BIST_CNTL_0 0x0028
+#define ixR300_MC_BIST_CNTL_1 0x0029
+#define ixR300_MC_BIST_CNTL_2 0x002a
+#define ixR300_MC_BIST_CNTL_3 0x002b
+#define ixR300_MC_BIST_CNTL_4 0x002c
+#define ixR300_MC_BIST_CNTL_5 0x002d
+#define ixR300_MC_IMP_STATUS 0x002e
+#define ixR300_MC_DLL_CNTL 0x002f
+#define NB_TOM 0x15C