+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }