+{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
+
+/* Spartan-3E devices */
+#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }