-#define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
-#define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
-#define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
-#define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
-#define NAND_SPAR_BUF0 (NFC_BASE + 0x800)
-#define NAND_SPAR_BUF1 (NFC_BASE + 0x810)
-#define NAND_SPAR_BUF2 (NFC_BASE + 0x820)
-#define NAND_SPAR_BUF3 (NFC_BASE + 0x830)
-#define NAND_RESERVED (NFC_BASE + 0x840)
+#define NFC_BUFSIZE_REG (NAND_REG_BASE + 0x00)
+#define RAM_BUFFER_ADDRESS_REG (NAND_REG_BASE + 0x04)
+#define NAND_FLASH_ADD_REG (NAND_REG_BASE + 0x06)
+#define NAND_FLASH_CMD_REG (NAND_REG_BASE + 0x08)
+#define NFC_CONFIGURATION_REG (NAND_REG_BASE + 0x0A)
+#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x0C)
+#define ECC_RSLT_MAIN_AREA_REG (NAND_REG_BASE + 0x0E)
+#define ECC_RSLT_SPARE_AREA_REG (NAND_REG_BASE + 0x10)
+#define NF_WR_PROT_REG (NAND_REG_BASE + 0x12)
+#define NAND_FLASH_WR_PR_ST_REG (NAND_REG_BASE + 0x18)
+#define NAND_FLASH_CONFIG1_REG (NAND_REG_BASE + 0x1A)
+#define NAND_FLASH_CONFIG2_REG (NAND_REG_BASE + 0x1C)
+#if defined(NFC_V1_1)
+#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x20)
+#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x22)
+#define UNLOCK_START_BLK_ADD1_REG (NAND_REG_BASE + 0x24)
+#define UNLOCK_END_BLK_ADD1_REG (NAND_REG_BASE + 0x26)
+#define UNLOCK_START_BLK_ADD2_REG (NAND_REG_BASE + 0x28)
+#define UNLOCK_END_BLK_ADD2_REG (NAND_REG_BASE + 0x2A)
+#define UNLOCK_START_BLK_ADD3_REG (NAND_REG_BASE + 0x2C)
+#define UNLOCK_END_BLK_ADD3_REG (NAND_REG_BASE + 0x2E)
+#else
+#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x14)
+#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x16)
+#endif