- u32 ret_val = 0, div;
- u32 pcdr0 = readl(SOC_CRM_PCDR0);
- u32 pcdr1 = readl(SOC_CRM_PCDR1);
- u32 cscr = readl(SOC_CRM_CSCR);
-
- switch (clk) {
- case PER_CLK1:
- div = (pcdr1 & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
- case PER_CLK2:
- case SPI1_CLK:
- case SPI2_CLK:
- div = ((pcdr1 >> 8) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
- case PER_CLK3:
- div = ((pcdr1 >> 16) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
- case PER_CLK4:
- div = ((pcdr1 >> 24) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
- case SSI1_BAUD:
- div = (pcdr0 >> 16) & 0x3F;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div += 4;
- }
- if ((cscr & (1 << 22)) != 0) {
- // This takes care of 0.5*SSIDIV[0] by x2
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
- case SSI2_BAUD:
- div = (pcdr0 >> 26) & 0x3F;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div += 4;
- }
- if ((cscr & (1 << 23)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
- case H264_BAUD:
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- div = (pcdr0 >> 8) & 0xF;
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div = (pcdr0 >> 10) & 0x3F;
- div += 4;
- }
- if ((cscr & (1 << 21)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
- case MSHC_BAUD:
- if ((cscr & (1 << 20)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- div = (pcdr0 & 0x1F) + 1;
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- div = (pcdr0 & 0x3F) + 1;
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- } else {
- div = (pcdr0 & 0x1F) + 1;
- ret_val = (2 * pll_clock(SER_PLL)) / div;
+ u32 ret_val = 0, div;
+ u32 pcdr0 = readl(SOC_CRM_PCDR0);
+ u32 pcdr1 = readl(SOC_CRM_PCDR1);
+ u32 cscr = readl(SOC_CRM_CSCR);
+
+ switch (clk) {
+ case PER_CLK1:
+ div = (pcdr1 & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ break;
+ case PER_CLK2:
+ case SPI1_CLK:
+ case SPI2_CLK:
+ div = ((pcdr1 >> 8) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ break;
+ case PER_CLK3:
+ div = ((pcdr1 >> 16) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ break;
+ case PER_CLK4:
+ div = ((pcdr1 >> 24) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ break;
+ case SSI1_BAUD:
+ div = (pcdr0 >> 16) & 0x3F;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div += 4;
+ }
+ if ((cscr & (1 << 22)) != 0) {
+ // This takes care of 0.5*SSIDIV[0] by x2
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
+ case SSI2_BAUD:
+ div = (pcdr0 >> 26) & 0x3F;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div += 4;
+ }
+ if ((cscr & (1 << 23)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
+ case H264_BAUD:
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ div = (pcdr0 >> 8) & 0xF;
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div = (pcdr0 >> 10) & 0x3F;
+ div += 4;
+ }
+ if ((cscr & (1 << 21)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
+ case MSHC_BAUD:
+ if ((cscr & (1 << 20)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ div = (pcdr0 & 0x1F) + 1;
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ div = (pcdr0 & 0x3F) + 1;
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ } else {
+ div = (pcdr0 & 0x1F) + 1;
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet\n",
+ __FUNCTION__, clk);
+ break;