-#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
-#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
-
-#define PART_NUMBER_OFFSET (12)
-#define MAJOR_NUMBER_OFFSET (4)
-#define MINOR_NUMBER_OFFSET (0)
-
-/* IOMUX defines */
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x108) // 0x108
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x10C) // 0x10c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x110) // 0x110
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x114) // 0x114
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x118) // 0x118
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x11C) // 0x11c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x120) // 0x120
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x124) // 0x124
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x128) // 0x128
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x12C) // 0x12c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x130) // 0x130
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x134) // 0x134
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x138) // 0x138
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x13C) // 0x13c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x140) // 0x140
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x144) // 0x144
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x148) // 0x148
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x14C) // 0x14c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x150) // 0x150
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x154) // 0x154
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x158) // 0x158
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x15C) // 0x15c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x160) // 0x160
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x164) // 0x164
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x168) // 0x168
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x16C) // 0x16c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x170) // 0x170
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x174) // 0x174
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x178) // 0x178
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x17C) // 0x17c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x180) // 0x180
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x184) // 0x184
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x188) // 0x188
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x18C) // 0x18c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x190) // 0x190
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x194) // 0x194
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x198) // 0x198
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x19C) // 0x19c
-
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x5B0) // 0x5b0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x5B4) // 0x5b4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x5B8) // 0x5b8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x5BC) // 0x5bc
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x5C0) // 0x5c0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x5C4) // 0x5c4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x5C8) // 0x5c8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x5CC) // 0x5cc
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x5D0) // 0x5d0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x5D4) // 0x5d4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x5D8) // 0x5d8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x5DC) // 0x5dc
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x5E0) // 0x5e0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x5E4) // 0x5e4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x5E8) // 0x5e8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x5EC) // 0x5ec
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x5F0) // 0x5f0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x5F4) // 0x5f4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x5F8) // 0x5f8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x5FC) // 0x5fc
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x600) // 0x600
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x604) // 0x604
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x608) // 0x608
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x60C) // 0x60c
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x610) // 0x610
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x614) // 0x614
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x618) // 0x618
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x61C) // 0x61c
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x620) // 0x620
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x624) // 0x624
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x628) // 0x628
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x62C) // 0x62c
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x630) // 0x630
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x634) // 0x634
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x638) // 0x638
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x63C) // 0x63c
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x640) // 0x640
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x644) // 0x644
-
-
-//#define BARKER_CODE_SWAP_LOC 0x404
-#define BARKER_CODE_VAL 0xB1
-#define NFC_V3_0 0x30