+/*
+CCM register set 0x53FD4000 0x53FD7FFF
+EIM register set 0x63FDA000 0x63FDAFFF
+NANDFC register set 0xF7FF0000 0xF7FFFFFF
+IOMUX Control (IOMUXC) registers 0x53FA8000 0x53FABFFF
+DPLLC1 register 0x63F80000 0x63F83FFF
+DPLLC2 register 0x63F84000 0x63F87FFF
+DPLLC3 register 0x63F88000 0x63F8BFFF
+DPLLC4 register 0x63F8C000 0x63F8FFFF
+ESD RAM controller register 0x63FD9000 0x63FD9FFF
+M4IF register 0x63FD8000 0x63FD8FFF
+DDR 0x70000000 0xEFFFFFFF
+EIM 0xF0000000 0xF7FEFFFF
+NANDFC Buffers 0xF7FF0000 0xF7FFFFFF
+IRAM Free Space 0xF8006000 0xF8017FF0
+GPU Memory 0xF8020000 0xF805FFFF
+*/
+#define CHECK_DCD_ADDR(a) ( \
+ ((a) >= 0x53fd4000 && (a) <= 0x53fd7fff) /* CCM */ || \
+ ((a) >= 0x63fda000 && (a) <= 0x63fdafff) /* EIM (CS0) */ || \
+ ((a) >= 0x53fa8000 && (a) <= 0x53fabfff) /* IOMUXC */ || \
+ ((a) >= 0x63f80000 && (a) <= 0x63f8ffff) /* DPLLC1..4 */ || \
+ ((a) >= 0x63fd8000 && (a) <= 0x63fd9fff) /* M4IF & SDRAM Contr. */ || \
+ ((a) >= 0x70000000 && (a) <= 0xefffffff) /* SDRAM */ || \
+ ((a) >= 0xf0000000 && (a) <= 0xf7ffffff) /* EIM & NANDFC buffers */ || \
+ ((a) >= 0xf8006000 && (a) <= 0xf8017ff0) /* IRAM free space */ || \
+ ((a) >= 0xf8020000 && (a) <= 0xf805ffff) /* GPU RAM */)
+
+ .macro mxc_dcd_item addr, val
+ .ifne CHECK_DCD_ADDR(\addr)
+ .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
+ .else
+ .error "Address \addr not accessible from DCD"
+ .endif
+ .endm
+
+#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)