coresight-etm4x: Controls pertaining to the selection of resources

[karo-tx-linux.git] / Documentation / ABI / testing / sysfs-bus-coresight-devices-etm4x

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
index c731ed9943b32120272116e047a7c824195b48a0..5c7391d4e33a08ae289c9d9956ea391899e9822b 100644 (file)
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
@@ -75,3 +75,170 @@ KernelVersion:      4.01
 Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:   (R) Indicates the number of single-shot comparator controls that
                are available for tracing.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/reset
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (W) Cancels all configuration on a trace unit and set it back
+               to its boot configuration.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mode
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls various modes supported by this ETM, for example
+               P0 instruction tracing, branch broadcast, cycle counting and
+               context ID tracing.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/pe
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls which PE to trace.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/event
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls the tracing of arbitrary events from bank 0 to 3.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/event_instren
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls the behavior of the events in bank 0 to 3.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/event_ts
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls the insertion of global timestamps in the trace
+               streams.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/syncfreq
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls how often trace synchronization requests occur.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Sets the threshold value for cycle counting.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls which regions in the memory map are enabled to
+               use branch broadcasting.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/event_vinst
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls instruction trace filtering.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) In Secure state, each bit controls whether instruction
+               tracing is enabled for the corresponding exception level.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) In non-secure state, each bit controls whether instruction
+               tracing is enabled for the corresponding exception level.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/addr_idx
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Select which address comparator or pair (of comparators) to
+               work with.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls what type of comparison the trace unit performs.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/addr_single
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Used to setup single address comparator values.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/addr_range
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Used to setup address range comparator values.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/seq_idx
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Select which sequensor.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/seq_state
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Use this to set, or read, the sequencer state.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/seq_event
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Moves the sequencer state to a specific state.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Moves the sequencer to state 0 when a programmed event
+               occurs.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Select which counter unit to work with.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) This sets or returns the reload count value of the
+               specific counter.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/cntr_val
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) This sets or returns the current count value of the
+                specific counter.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls the operation of the selected counter.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/res_idx
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Select which resource selection unit to work with.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (RW) Controls the selection of the resources in the trace unit.