pci: Add PCIe driver for Samsung Exynos

[karo-tx-linux.git] / Documentation / devicetree / bindings / pci / designware-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
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+* Synopsis Designware PCIe interface
+
+Required properties:
+- compatible: should contain "snps,dw-pcie" to identify the
+       core, plus an identifier for the specific instance, such
+       as "samsung,exynos5440-pcie".
+- reg: base addresses and lengths of the pcie controller,
+       the phy controller, additional register for the phy controller.
+- interrupts: interrupt values for level interrupt,
+       pulse interrupt, special interrupt.
+- clocks: from common clock binding: handle to pci clock.
+- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- device_type: set to "pci"
+- ranges: ranges for the PCI memory and I/O regions
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map: standard PCI properties
+       to define the mapping of the PCIe interface to interrupt
+       numbers.
+- reset-gpio: gpio pin number of power good signal
+
+Example:
+
+SoC specific DT Entry:
+
+       pcie@290000 {
+               compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+               reg = <0x290000 0x1000
+                       0x270000 0x1000
+                       0x271000 0x40>;
+               interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+               clocks = <&clock 28>, <&clock 27>;
+               clock-names = "pcie", "pcie_bus";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               device_type = "pci";
+               ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
+                         0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
+                         0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0>;
+               interrupt-map = <0x0 0 &gic 53>;
+       };
+
+       pcie@2a0000 {
+               compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+               reg = <0x2a0000 0x1000
+                       0x272000 0x1000
+                       0x271040 0x40>;
+               interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+               clocks = <&clock 29>, <&clock 27>;
+               clock-names = "pcie", "pcie_bus";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               device_type = "pci";
+               ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
+                         0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
+                         0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0>;
+               interrupt-map = <0x0 0 &gic 56>;
+       };
+
+Board specific DT Entry:
+
+       pcie@290000 {
+               reset-gpio = <&pin_ctrl 5 0>;
+       };
+
+       pcie@2a0000 {
+               reset-gpio = <&pin_ctrl 22 0>;
+       };