Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[karo-tx-uboot.git] / README

diff --git a/README b/README
index f91e0442ad45d8cff50f2c1f8420ba95aad5ce40..12758dc6e793f3fb27b0520ea7127788921308a2 100644 (file)
--- a/README
+++ b/README
@@ -431,6 +431,14 @@ The following options need to be configured:
                In this mode, a single differential clock is used to supply
                clocks to the sysclock, ddrclock and usbclock.
 
+               CONFIG_SYS_CPC_REINIT_F
+               This CONFIG is defined when the CPC is configured as SRAM at the
+               time of U-boot entry and is required to be re-initialized.
+
+               CONFIG_DEEP_SLEEP
+               Inidcates this SoC supports deep sleep feature. If deep sleep is
+               supported, core will start to execute uboot when wakes up.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -458,6 +466,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DDRC_GEN3
                Freescale DDR3 controller.
 
+               CONFIG_SYS_FSL_DDRC_GEN4
+               Freescale DDR4 controller.
+
                CONFIG_SYS_FSL_DDRC_ARM_GEN3
                Freescale DDR3 controller for ARM-based SoCs.
 
@@ -473,7 +484,15 @@ The following options need to be configured:
 
                CONFIG_SYS_FSL_DDR3
                Board config to use DDR3. It can be enabled for SoCs with
-               Freescale DDR3 controllers.
+               Freescale DDR3 or DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR3L
+               Board config to use DDR3L. It can be enabled for SoCs with
+               DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR4
+               Board config to use DDR4. It can be enabled for SoCs with
+               DDR4 controllers.
 
                CONFIG_SYS_FSL_IFC_BE
                Defines the IFC controller register space as Big Endian
@@ -490,6 +509,10 @@ The following options need to be configured:
                PBI commands can be used to configure SoC before it starts the execution.
                Please refer doc/README.pblimage for more details
 
+               CONFIG_SPL_FSL_PBL
+               It adds a target to create boot binary having SPL binary in PBI format
+               concatenated with u-boot binary.
+
                CONFIG_SYS_FSL_DDR_BE
                Defines the DDR controller register space as Big Endian
 
@@ -3317,6 +3340,9 @@ FIT uImage format:
                continuing (the hardware starts execution after just
                loading the first page rather than the full 4K).
 
+               CONFIG_SPL_SKIP_RELOCATE
+               Avoid SPL relocation
+
                CONFIG_SPL_NAND_BASE
                Include nand_base.c in the SPL.  Requires
                CONFIG_SPL_NAND_DRIVERS.
@@ -4502,8 +4528,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 
-- CONFIG_SYS_QE_FMAN_FW_ADDR
-       The address in the storage device where the firmware is located.  The
+- CONFIG_SYS_FMAN_FW_ADDR
+       The address in the storage device where the FMAN microcode is located.  The
+       meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+       is also specified.
+
+- CONFIG_SYS_QE_FW_ADDR
+       The address in the storage device where the QE microcode is located.  The
        meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
        is also specified.