omap-common/hwinit-common.c: timer_init() doesn't need to touch gd

[karo-tx-uboot.git] / README

diff --git a/README b/README
index 42ece994739cd4f56f39e32861d57c78503bc3bc..00cd05520c1f02c77b6655641034aadf132c1f4c 100644 (file)
--- a/README
+++ b/README
@@ -186,7 +186,6 @@ Directory Hierarchy:
       /mpc5xx          Files specific to Freescale MPC5xx CPUs
       /mpc5xxx         Files specific to Freescale MPC5xxx CPUs
       /mpc8xx          Files specific to Freescale MPC8xx CPUs
-      /mpc824x         Files specific to Freescale MPC824x CPUs
       /mpc8260         Files specific to Freescale MPC8260 CPUs
       /mpc85xx         Files specific to Freescale MPC85xx CPUs
       /ppc4xx          Files specific to AMCC PowerPC 4xx CPUs
@@ -326,10 +325,6 @@ The following options need to be configured:
                                          multiple fs option at one time
                                          for marvell soc family
 
-- MPC824X Family Member (if CONFIG_MPC824X is defined)
-               Define exactly one of
-               CONFIG_MPC8240, CONFIG_MPC8245
-
 - 8xx CPU Options: (if using an MPC8xx CPU)
                CONFIG_8xx_GCLK_FREQ    - deprecated: CPU clock if
                                          get_gclk_freq() cannot work
@@ -4016,6 +4011,25 @@ Configuration Settings:
                boards which do not use the full malloc in SPL (which is
                enabled with CONFIG_SYS_SPL_MALLOC_START).
 
+- CONFIG_SYS_NONCACHED_MEMORY:
+               Size of non-cached memory area. This area of memory will be
+               typically located right below the malloc() area and mapped
+               uncached in the MMU. This is useful for drivers that would
+               otherwise require a lot of explicit cache maintenance. For
+               some drivers it's also impossible to properly maintain the
+               cache. For example if the regions that need to be flushed
+               are not a multiple of the cache-line size, *and* padding
+               cannot be allocated between the regions to align them (i.e.
+               if the HW requires a contiguous array of regions, and the
+               size of each region is not cache-aligned), then a flush of
+               one region may result in overwriting data that hardware has
+               written to another region in the same cache-line. This can
+               happen for example in network drivers where descriptors for
+               buffers are typically smaller than the CPU cache-line (e.g.
+               16 bytes vs. 32 or 64 bytes).
+
+               Non-cached memory is only supported on 32-bit ARM at present.
+
 - CONFIG_SYS_BOOTM_LEN:
                Normally compressed uImages are limited to an
                uncompressed size of 8 MBytes. If this is not enough,