powerpc/fsl-corenet: work around erratum A004510

[karo-tx-uboot.git] / README

diff --git a/README b/README
index 81ee7d4d7374bac9306d5ba3ee39766d43b54e99..8197235a37206885199b308bcadd419bb2cccf14 100644 (file)
--- a/README
+++ b/README
@@ -383,6 +383,31 @@ The following options need to be configured:
                symbol should be set to the TLB1 entry to be used for this
                purpose.
 
+               CONFIG_SYS_FSL_ERRATUM_A004510
+
+               Enables a workaround for erratum A004510.  If set,
+               then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
+               CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+
+               CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
+               CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
+
+               Defines one or two SoC revisions (low 8 bits of SVR)
+               for which the A004510 workaround should be applied.
+
+               The rest of SVR is either not relevant to the decision
+               of whether the erratum is present (e.g. p2040 versus
+               p2041) or is implied by the build target, which controls
+               whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
+
+               See Freescale App Note 4493 for more information about
+               this erratum.
+
+               CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+
+               This is the value to write into CCSR offset 0x18600
+               according to the A004510 workaround.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN