#
-# (C) Copyright 2000 - 2011
+# (C) Copyright 2000 - 2012
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
XWAY SoCs for booting from NOR flash. The U-Boot image needs to
be swapped if a flash programmer is used.
+- ARM options:
+ CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+
+ Select high exception vectors of the ARM core, e.g., do not
+ clear the V bit of the c1 register of CP15.
+
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
CONFIG_CFB_CONSOLE
Enables console device for a color framebuffer. Needs following
- defines (cf. smiLynxEM, i8042, board/eltec/bab7xx)
+ defines (cf. smiLynxEM, i8042)
VIDEO_FB_LITTLE_ENDIAN graphic memory organisation
(default big endian)
VIDEO_HW_RECTFILL graphic chip supports
'Sane' compilers will generate smaller code if
CONFIG_PRE_CON_BUF_SZ is a power of 2
+- Safe printf() functions
+ Define CONFIG_SYS_VSNPRINTF to compile in safe versions of
+ the printf() functions. These are defined in
+ include/vsprintf.h and include snprintf(), vsnprintf() and
+ so on. Code size increase is approximately 300-500 bytes.
+ If this option is not given then these functions will
+ silently discard their buffer size argument - this means
+ you are not getting any overflow checking in this case.
+
- Boot Delay: CONFIG_BOOTDELAY - in seconds
Delay before automatically booting the default image;
set to -1 to disable autoboot.
(requires CONFIG_CMD_I2C)
CONFIG_CMD_SETGETDCR Support for DCR Register access
(4xx only)
+ CONFIG_CMD_SF * Read/write/erase SPI NOR flash
CONFIG_CMD_SHA1SUM print sha1 memory digest
(requires CONFIG_CMD_MEMORY)
CONFIG_CMD_SOURCE "source" command Support
CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx
CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
- CONFIG_RTC_MC13783 - use MC13783 RTC
+ CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC
CONFIG_RTC_MC146818 - use MC146818 RTC
CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC
CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC
- NETWORK Support (PCI):
CONFIG_E1000
- Support for Intel 8254x gigabit chips.
+ Support for Intel 8254x/8257x gigabit chips.
+
+ CONFIG_E1000_SPI
+ Utility code for direct access to the SPI bus on Intel 8257x.
+ This does not do anything useful unless you set at least one
+ of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
+
+ CONFIG_E1000_SPI_GENERIC
+ Allow generic access to the SPI bus on the Intel 8257x, for
+ example with the "sspi" command.
+
+ CONFIG_CMD_E1000
+ Management command for E1000 devices. When used on devices
+ with SPI support you can reprogram the EEPROM from U-Boot.
CONFIG_E1000_FALLBACK_MAC
default MAC for empty EEPROM after production.
If this defined, the driver is quiet.
The driver doen't show link status messages.
+ CONFIG_CALXEDA_XGMAC
+ Support for the Calxeda XGMAC device
+
CONFIG_DRIVER_LAN91C96
Support for SMSC's LAN91C96 chips.
Define this to use i/o functions instead of macros
(some hardware wont work with macros)
+ CONFIG_DRIVER_TI_EMAC
+ Support for davinci emac
+
+ CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
+ Define this if you have more then 3 PHYs.
+
CONFIG_FTGMAC100
Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
CONFIG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
+- TPM Support:
+ CONFIG_GENERIC_LPC_TPM
+ Support for generic parallel port TPM devices. Only one device
+ per system is supported at this time.
+
+ CONFIG_TPM_TIS_BASE_ADDRESS
+ Base address where the generic TPM device is mapped
+ to. Contemporary x86 systems usually map it at
+ 0xfed40000.
+
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
May be defined to allow interrupt polling
instead of using asynchronous interrupts
+ CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
+ txfilltuning field in the EHCI controller on reset.
+
- USB Device:
Define the below if you wish to use the USB console.
Once firmware is rebuilt from a serial console issue the
for your device
- CONFIG_USBD_PRODUCTID 0xFFFF
+- ULPI Layer Support:
+ The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
+ the generic ULPI layer. The generic layer accesses the ULPI PHY
+ via the platform viewport, so you need both the genric layer and
+ the viewport enabled. Currently only Chipidea/ARC based
+ viewport is supported.
+ To enable the ULPI layer support, define CONFIG_USB_ULPI and
+ CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
- MMC Support:
The MMC controller on the Intel PXA is supported. To
- FAT(File Allocation Table) filesystem write function support:
CONFIG_FAT_WRITE
- Support for saving memory data as a file
- in FAT formatted partition
+
+ Define this to enable support for saving memory data as a
+ file in FAT formatted partition.
+
+ This will also enable the command "fatwrite" enabling the
+ user to write files to FAT.
- Keyboard Support:
CONFIG_ISA_KEYBOARD
CONFIG_MXC_SPI
Enables the driver for the SPI controllers on i.MX and MXC
- SoCs. Currently only i.MX31 is supported.
+ SoCs. Currently i.MX31/35/51 are supported.
- FPGA Support: CONFIG_FPGA
allows to read/write in Dataflash via the standard
commands cp, md...
+- Serial Flash support
+ CONFIG_CMD_SF
+
+ Defining this option enables SPI flash commands
+ 'sf probe/read/write/erase/update'.
+
+ Usage requires an initial 'probe' to define the serial
+ flash parameters, followed by read/write/erase/update
+ commands.
+
+ The following defaults may be provided by the platform
+ to handle the common case when only a single serial
+ flash is present on the system.
+
+ CONFIG_SF_DEFAULT_BUS Bus identifier
+ CONFIG_SF_DEFAULT_CS Chip-select
+ CONFIG_SF_DEFAULT_MODE (see include/spi.h)
+ CONFIG_SF_DEFAULT_SPEED in Hz
+
- SystemACE Support:
CONFIG_SYSTEMACE
example, some LED's) on your board. At the moment,
the following checkpoints are implemented:
+- Detailed boot stage timing
+ CONFIG_BOOTSTAGE
+ Define this option to get detailed timing of each stage
+ of the boot process.
+
+ CONFIG_BOOTSTAGE_USER_COUNT
+ This is the number of available user bootstage records.
+ Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
+ a new ID will be allocated from this stash. If you exceed
+ the limit, recording will stop.
+
+ CONFIG_BOOTSTAGE_REPORT
+ Define this to print a report before boot, similar to this:
+
+ Timer summary in microseconds:
+ Mark Elapsed Stage
+ 0 0 reset
+ 3,575,678 3,575,678 board_init_f start
+ 3,575,695 17 arch_cpu_init A9
+ 3,575,777 82 arch_cpu_init done
+ 3,659,598 83,821 board_init_r start
+ 3,910,375 250,777 main_loop
+ 29,916,167 26,005,792 bootm_start
+ 30,361,327 445,160 start_kernel
+
Legacy uImage format:
Arg Where When
CONFIG_SPL
Enable building of SPL globally.
+ CONFIG_SPL_LDSCRIPT
+ LDSCRIPT for linking the SPL binary.
+
+ CONFIG_SPL_MAX_SIZE
+ Maximum binary size (text, data and rodata) of the SPL binary.
+
CONFIG_SPL_TEXT_BASE
TEXT_BASE for linking the SPL binary.
- CONFIG_SPL_LDSCRIPT
- LDSCRIPT for linking the SPL binary.
+ CONFIG_SPL_BSS_START_ADDR
+ Link address for the BSS within the SPL binary.
+
+ CONFIG_SPL_BSS_MAX_SIZE
+ Maximum binary size of the BSS section of the SPL binary.
+
+ CONFIG_SPL_STACK
+ Adress of the start of the stack SPL will use
+
+ CONFIG_SYS_SPL_MALLOC_START
+ Starting address of the malloc pool used in SPL.
+
+ CONFIG_SYS_SPL_MALLOC_SIZE
+ The size of the malloc pool used in SPL.
CONFIG_SPL_LIBCOMMON_SUPPORT
Support for common/libcommon.o in SPL binary
CONFIG_SPL_MMC_SUPPORT
Support for drivers/mmc/libmmc.o in SPL binary
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+ CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
+ CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION
+ Address, size and partition on the MMC to load U-Boot from
+ when the MMC is being used in raw mode.
+
+ CONFIG_SPL_FAT_SUPPORT
+ Support for fs/fat/libfat.o in SPL binary
+
+ CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
+ Filename to read to load U-Boot when reading from FAT
+
+ CONFIG_SPL_NAND_SIMPLE
+ Support for drivers/mtd/nand/libnand.o in SPL binary
+
+ CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
+ CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
+ CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
+ CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
+ CONFIG_SYS_NAND_ECCBYTES
+ Defines the size and behavior of the NAND that SPL uses
+ to read U-Boot with CONFIG_SPL_NAND_SIMPLE
+
+ CONFIG_SYS_NAND_U_BOOT_OFFS
+ Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot
+ from.
+
+ CONFIG_SYS_NAND_U_BOOT_START
+ Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot
+ to.
+
+ CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+ Define this if you need to first read the OOB and then the
+ data. This is used for example on davinci plattforms.
+
+ CONFIG_SPL_OMAP3_ID_NAND
+ Support for an OMAP3-specific set of functions to return the
+ ID and MFR of the first attached NAND chip, if present.
+
CONFIG_SPL_SERIAL_SUPPORT
Support for drivers/serial/libserial.o in SPL binary
CONFIG_SPL_SPI_SUPPORT
Support for drivers/spi/libspi.o in SPL binary
- CONFIG_SPL_FAT_SUPPORT
- Support for fs/fat/libfat.o in SPL binary
-
CONFIG_SPL_LIBGENERIC_SUPPORT
Support for lib/libgeneric.o in SPL binary
be used if available. These functions may be faster under some
conditions but may increase the binary size.
+Freescale QE/FMAN Firmware Support:
+-----------------------------------
+
+The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
+loading of "firmware", which is encoded in the QE firmware binary format.
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_SYS_QE_FMAN_FW_ADDR
+ The address in the storage device where the firmware is located. The
+ meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ is also specified.
+
+- CONFIG_SYS_QE_FMAN_FW_LENGTH
+ The maximum possible size of the firmware. The firmware binary format
+ has a field that specifies the actual size of the firmware, but it
+ might not be possible to read any part of the firmware unless some
+ local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NOR
+ Specifies that QE/FMAN firmware is located in NOR flash, mapped as
+ normal addressable memory via the LBC. CONFIG_SYS_FMAN_FW_ADDR is the
+ virtual address in NOR flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NAND
+ Specifies that QE/FMAN firmware is located in NAND flash.
+ CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_MMC
+ Specifies that QE/FMAN firmware is located on the primary SD/MMC
+ device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+ Specifies that QE/FMAN firmware is located on the primary SPI
+ device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+
Building the Software:
======================
fdt_high - if set this restricts the maximum address that the
flattened device tree will be copied into upon boot.
+ For example, if you have a system with 1 GB memory
+ at physical address 0x10000000, while Linux kernel
+ only recognizes the first 704 MB as low memory, you
+ may need to set fdt_high as 0x3C000000 to have the
+ device tree blob be copied to the maximum address
+ of the 704 MB low memory, so that Linux kernel can
+ access it during the boot procedure.
+
If this is set to the special value 0xFFFFFFFF then
the fdt will not be copied at all on boot. For this
to work it must reside in writable memory, have