exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+ COUNTER_FREQUENCY
+ Generic timer clock source frequency.
+
+ COUNTER_FREQUENCY_REAL
+ Generic timer clock source frequency if the real clock is
+ different from COUNTER_FREQUENCY, and can only be determined
+ at run time.
+
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
boot. See the documentation file README.video for a
description of this variable.
- CONFIG_VIDEO_VGA
-
- Enable the VGA video / BIOS for x86. The alternative if you
- are using coreboot is to use the coreboot frame buffer
- driver.
-
- Keyboard Support:
CONFIG_KEYBOARD
- define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
If those defines are not set, default value is 100000
for speed, and 0 for slave.
+ - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
+ - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
- drivers/i2c/rcar_i2c.c:
- activate this driver with CONFIG_SYS_I2C_RCAR
memories can be connected with a given cs line.
Currently Xilinx Zynq qspi supports these type of connections.
- CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
- enable the W#/Vpp signal to disable writing to the status
- register on ST MICRON flashes like the N25Q128.
- The status register write enable/disable bit, combined with
- the W#/VPP signal provides hardware data protection for the
- device as follows: When the enable/disable bit is set to 1,
- and the W#/VPP signal is driven LOW, the status register
- nonvolatile bits become read-only and the WRITE STATUS REGISTER
- operation will not execute. The only way to exit this
- hardware-protected mode is to drive W#/VPP HIGH.
-
- SystemACE Support:
CONFIG_SYSTEMACE
example, some LED's) on your board. At the moment,
the following checkpoints are implemented:
-- Detailed boot stage timing
- CONFIG_BOOTSTAGE
- Define this option to get detailed timing of each stage
- of the boot process.
-
- CONFIG_BOOTSTAGE_USER_COUNT
- This is the number of available user bootstage records.
- Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
- a new ID will be allocated from this stash. If you exceed
- the limit, recording will stop.
-
- CONFIG_BOOTSTAGE_REPORT
- Define this to print a report before boot, similar to this:
-
- Timer summary in microseconds:
- Mark Elapsed Stage
- 0 0 reset
- 3,575,678 3,575,678 board_init_f start
- 3,575,695 17 arch_cpu_init A9
- 3,575,777 82 arch_cpu_init done
- 3,659,598 83,821 board_init_r start
- 3,910,375 250,777 main_loop
- 29,916,167 26,005,792 bootm_start
- 30,361,327 445,160 start_kernel
-
- CONFIG_CMD_BOOTSTAGE
- Add a 'bootstage' command which supports printing a report
- and un/stashing of bootstage data.
-
- CONFIG_BOOTSTAGE_FDT
- Stash the bootstage information in the FDT. A root 'bootstage'
- node is created with each bootstage id as a child. Each child
- has a 'name' property and either 'mark' containing the
- mark time in microsecond, or 'accum' containing the
- accumulated time for that bootstage id in microseconds.
- For example:
-
- bootstage {
- 154 {
- name = "board_init_f";
- mark = <3575678>;
- };
- 170 {
- name = "lcd";
- accum = <33482>;
- };
- };
-
- Code in the Linux kernel can find this in /proc/devicetree.
Legacy uImage format:
- CONFIG_FSL_DDR_SYNC_REFRESH
Enable sync of refresh for multiple controllers.
+- CONFIG_FSL_DDR_BIST
+ Enable built-in memory test for Freescale DDR controllers.
+
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
flash or offset in NAND flash.
*Note* - these variables don't have to be defined for all boards, some
-boards currenlty use other variables for these purposes, and some
+boards currently use other variables for these purposes, and some
boards use these variables for other purposes.
Image File Name RAM Address Flash Location