Merge tag 'tags/soc_for_v3.10' into mvebu/dt

[karo-tx-linux.git] / arch / arm / boot / dts / armada-xp-db.dts

diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 8e53b25b55084ed3b8712156f21d357510be207c..54cc5bb705fb0e1fcb38bbd2d82340ec28473533 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -90,5 +90,69 @@
                        phy = <&phy3>;
                        phy-mode = "sgmii";
                };
+
+               mvsdio@d00d4000 {
+                       pinctrl-0 = <&sdio_pins>;
+                       pinctrl-names = "default";
+                       status = "okay";
+                       /* No CD or WP GPIOs */
+               };
+
+               usb@d0050000 {
+                       status = "okay";
+               };
+
+               usb@d0051000 {
+                       status = "okay";
+               };
+
+               usb@d0052000 {
+                       status = "okay";
+               };
+
+               spi0: spi@d0010600 {
+                       status = "okay";
+
+                       spi-flash@0 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "m25p64";
+                               reg = <0>; /* Chip select 0 */
+                               spi-max-frequency = <20000000>;
+                       };
+               };
+
+               pcie-controller {
+                       status = "okay";
+
+                       /*
+                        * All 6 slots are physically present as
+                        * standard PCIe slots on the board.
+                        */
+                       pcie@1,0 {
+                               /* Port 0, Lane 0 */
+                               status = "okay";
+                       };
+                       pcie@2,0 {
+                               /* Port 0, Lane 1 */
+                               status = "okay";
+                       };
+                       pcie@3,0 {
+                               /* Port 0, Lane 2 */
+                               status = "okay";
+                       };
+                       pcie@4,0 {
+                               /* Port 0, Lane 3 */
+                               status = "okay";
+                       };
+                       pcie@9,0 {
+                               /* Port 2, Lane 0 */
+                               status = "okay";
+                       };
+                       pcie@10,0 {
+                               /* Port 3, Lane 0 */
+                               status = "okay";
+                       };
+               };
        };
 };