Merge remote-tracking branch 'tip/timers/core' into fordlezcano/3.13/sched-clock64...

[karo-tx-linux.git] / arch / arm / boot / dts / armada-xp-gp.dts

diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index c87b2de29c30161a1c032c21d80c07c422ecb2f6..2298e4a910e230748dda13cb70cab55713932a10 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -14,7 +14,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
 
 / {
        model = "Marvell Armada XP Development Board DB-MV784MP-GP";
@@ -39,9 +39,58 @@
        };
 
        soc {
-               ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
-                         0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
-                         0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                         MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+               devbus-bootcs {
+                       status = "okay";
+
+                       /* Device Bus parameters are required */
+
+                       /* Read parameters */
+                       devbus,bus-width    = <8>;
+                       devbus,turn-off-ps  = <60000>;
+                       devbus,badr-skew-ps = <0>;
+                       devbus,acc-first-ps = <124000>;
+                       devbus,acc-next-ps  = <248000>;
+                       devbus,rd-setup-ps  = <0>;
+                       devbus,rd-hold-ps   = <0>;
+
+                       /* Write parameters */
+                       devbus,sync-enable = <0>;
+                       devbus,wr-high-ps  = <60000>;
+                       devbus,wr-low-ps   = <60000>;
+                       devbus,ale-wr-ps   = <60000>;
+
+                       /* NOR 16 MiB */
+                       nor@0 {
+                               compatible = "cfi-flash";
+                               reg = <0 0x1000000>;
+                               bank-width = <2>;
+                       };
+               };
+
+               pcie-controller {
+                       status = "okay";
+
+                       /*
+                        * The 3 slots are physically present as
+                        * standard PCIe slots on the board.
+                        */
+                       pcie@1,0 {
+                               /* Port 0, Lane 0 */
+                               status = "okay";
+                       };
+                       pcie@9,0 {
+                               /* Port 2, Lane 0 */
+                               status = "okay";
+                       };
+                       pcie@10,0 {
+                               /* Port 3, Lane 0 */
+                               status = "okay";
+                       };
+               };
 
                internal-regs {
                        serial@12000 {
@@ -126,56 +175,6 @@
                                        spi-max-frequency = <108000000>;
                                };
                        };
-
-                       devbus-bootcs@10400 {
-                               status = "okay";
-                               ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
-
-                               /* Device Bus parameters are required */
-
-                               /* Read parameters */
-                               devbus,bus-width    = <8>;
-                               devbus,turn-off-ps  = <60000>;
-                               devbus,badr-skew-ps = <0>;
-                               devbus,acc-first-ps = <124000>;
-                               devbus,acc-next-ps  = <248000>;
-                               devbus,rd-setup-ps  = <0>;
-                               devbus,rd-hold-ps   = <0>;
-
-                               /* Write parameters */
-                               devbus,sync-enable = <0>;
-                               devbus,wr-high-ps  = <60000>;
-                               devbus,wr-low-ps   = <60000>;
-                               devbus,ale-wr-ps   = <60000>;
-
-                               /* NOR 16 MiB */
-                               nor@0 {
-                                       compatible = "cfi-flash";
-                                       reg = <0 0x1000000>;
-                                       bank-width = <2>;
-                               };
-                       };
-
-                       pcie-controller {
-                               status = "okay";
-
-                               /*
-                                * The 3 slots are physically present as
-                                * standard PCIe slots on the board.
-                                */
-                               pcie@1,0 {
-                                       /* Port 0, Lane 0 */
-                                       status = "okay";
-                               };
-                               pcie@9,0 {
-                                       /* Port 2, Lane 0 */
-                                       status = "okay";
-                               };
-                               pcie@10,0 {
-                                       /* Port 3, Lane 0 */
-                                       status = "okay";
-                               };
-                       };
                };
        };
 };