ARM: dts: mvebu: Convert all the mvebu files to use the range property

[karo-tx-linux.git] / arch / arm / boot / dts / armada-xp-mv78260.dtsi

diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 9e23bd8c9536d9b3d02c14a275efad5111d03f4a..1faacd13d51402205a77554746fb2938a89cc58a 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -26,33 +26,39 @@
        };
 
        cpus {
-           #address-cells = <1>;
-           #size-cells = <0>;
-
-           cpu@0 {
-               device_type = "cpu";
-               compatible = "marvell,sheeva-v7";
-               reg = <0>;
-               clocks = <&cpuclk 0>;
-           };
-
-           cpu@1 {
-               device_type = "cpu";
-               compatible = "marvell,sheeva-v7";
-               reg = <1>;
-               clocks = <&cpuclk 1>;
-           };
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "marvell,sheeva-v7";
+                       reg = <0>;
+                       clocks = <&cpuclk 0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "marvell,sheeva-v7";
+                       reg = <1>;
+                       clocks = <&cpuclk 1>;
+               };
        };
 
        soc {
                pinctrl {
                        compatible = "marvell,mv78260-pinctrl";
-                       reg = <0xd0018000 0x38>;
+                       reg = <0x18000 0x38>;
+
+                       sdio_pins: sdio-pins {
+                               marvell,pins = "mpp30", "mpp31", "mpp32",
+                                              "mpp33", "mpp34", "mpp35";
+                               marvell,function = "sd0";
+                       };
                };
 
-               gpio0: gpio@d0018100 {
+               gpio0: gpio@18100 {
                        compatible = "marvell,orion-gpio";
-                       reg = <0xd0018100 0x40>;
+                       reg = <0x18100 0x40>;
                        ngpios = <32>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -61,9 +67,9 @@
                        interrupts = <82>, <83>, <84>, <85>;
                };
 
-               gpio1: gpio@d0018140 {
+               gpio1: gpio@18140 {
                        compatible = "marvell,orion-gpio";
-                       reg = <0xd0018140 0x40>;
+                       reg = <0x18140 0x40>;
                        ngpios = <32>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -72,9 +78,9 @@
                        interrupts = <87>, <88>, <89>, <90>;
                };
 
-               gpio2: gpio@d0018180 {
+               gpio2: gpio@18180 {
                        compatible = "marvell,orion-gpio";
-                       reg = <0xd0018180 0x40>;
+                       reg = <0x18180 0x40>;
                        ngpios = <3>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -83,12 +89,134 @@
                        interrupts = <91>;
                };
 
-               ethernet@d0034000 {
+               ethernet@34000 {
                                compatible = "marvell,armada-370-neta";
-                               reg = <0xd0034000 0x2500>;
+                               reg = <0x34000 0x2500>;
                                interrupts = <14>;
                                clocks = <&gateclk 1>;
                                status = "disabled";
                };
+
+               /*
+                * MV78260 has 3 PCIe units Gen2.0: Two units can be
+                * configured as x4 or quad x1 lanes. One unit is
+                * x4/x1.
+                */
+               pcie-controller {
+                       compatible = "marvell,armada-xp-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                 0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                 0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                 0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                 0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                 0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
+                                 0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
+                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 58>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 5>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 59>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <1>;
+                               clocks = <&gateclk 6>;
+                               status = "disabled";
+                       };
+
+                       pcie@3,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                               reg = <0x1800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 60>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <2>;
+                               clocks = <&gateclk 7>;
+                               status = "disabled";
+                       };
+
+                       pcie@4,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+                               reg = <0x2000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 61>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <3>;
+                               clocks = <&gateclk 8>;
+                               status = "disabled";
+                       };
+
+                       pcie@9,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+                               reg = <0x4800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 99>;
+                               marvell,pcie-port = <2>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 26>;
+                               status = "disabled";
+                       };
+
+                       pcie@10,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
+                               reg = <0x5000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 103>;
+                               marvell,pcie-port = <3>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 27>;
+                               status = "disabled";
+                       };
+               };
        };
 };