ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates

[karo-tx-linux.git] / arch / arm / boot / dts / dra7xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3330738e4c6e1064a9f34fc5f78a1adfb58cd6f4..76e2b747814112a50bce824d9f26a02ffdf0addb 100644 (file)
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -338,6 +338,8 @@
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
                reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+               assigned-clocks = <&dpll_dsp_ck>;
+               assigned-clock-rates = <600000000>;
        };
 
        dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
@@ -349,6 +351,8 @@
                reg = <0x0244>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               assigned-clocks = <&dpll_dsp_m2_ck>;
+               assigned-clock-rates = <600000000>;
        };
 
        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
@@ -372,6 +376,8 @@
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+               assigned-clocks = <&dpll_iva_ck>;
+               assigned-clock-rates = <1165000000>;
        };
 
        dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
@@ -383,6 +389,8 @@
                reg = <0x01b0>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               assigned-clocks = <&dpll_iva_m2_ck>;
+               assigned-clock-rates = <388333334>;
        };
 
        iva_dclk: iva_dclk {
@@ -659,6 +667,8 @@
                reg = <0x0248>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               assigned-clocks = <&dpll_dsp_m3x2_ck>;
+               assigned-clock-rates = <400000000>;
        };
 
        dpll_gmac_x2_ck: dpll_gmac_x2_ck {
@@ -791,6 +801,8 @@
                clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
                ti,bit-shift = <24>;
                reg = <0x0520>;
+               assigned-clocks = <&ipu1_gfclk_mux>;
+               assigned-clock-parents = <&dpll_core_h22x2_ck>;
        };
 
        mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {