Merge tag 'dlm-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/teigland/linux-dlm

[karo-tx-linux.git] / arch / arm / boot / dts / mt8135.dtsi

diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 0aba9eb28e2b4fd0e476f114ff72402e939a37b6..08371dbae543d8e8c07be0477db16d27ca46c559 100644 (file)
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -12,8 +12,10 @@
  * GNU General Public License for more details.
  */
 
+#include <dt-bindings/clock/mt8135-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset-controller/mt8135-resets.h>
 #include "skeleton64.dtsi"
 #include "mt8135-pinfunc.h"
 
@@ -88,12 +90,11 @@
                        #clock-cells = <0>;
                };
 
-               uart_clk: dummy26m {
+               clk26m: clk26m {
                        compatible = "fixed-clock";
-                       clock-frequency = <26000000>;
                        #clock-cells = <0>;
+                       clock-frequency = <26000000>;
                };
-
        };
 
        soc {
@@ -102,6 +103,26 @@
                compatible = "simple-bus";
                ranges;
 
+               topckgen: topckgen@10000000 {
+                       compatible = "mediatek,mt8135-topckgen";
+                       reg = <0 0x10000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               infracfg: infracfg@10001000 {
+                       #reset-cells = <1>;
+                       #clock-cells = <1>;
+                       compatible = "mediatek,mt8135-infracfg", "syscon";
+                       reg = <0 0x10001000 0 0x1000>;
+               };
+
+               pericfg: pericfg@10003000 {
+                       #reset-cells = <1>;
+                       #clock-cells = <1>;
+                       compatible = "mediatek,mt8135-pericfg", "syscon";
+                       reg = <0 0x10003000 0 0x1000>;
+               };
+
                /*
                 * Pinctrl access register at 0x10005000 and 0x1020c000 through
                 * regmap. Register 0x1000b000 is used by EINT.
@@ -134,6 +155,19 @@
                        clock-names = "system-clk", "rtc-clk";
                };
 
+               pwrap: pwrap@1000f000 {
+                       compatible = "mediatek,mt8135-pwrap";
+                       reg = <0 0x1000f000 0 0x1000>,
+                               <0 0x11017000 0 0x1000>;
+                       reg-names = "pwrap", "pwrap-bridge";
+                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
+                                       <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+                       reset-names = "pwrap", "pwrap-bridge";
+                       clocks = <&clk26m>, <&clk26m>;
+                       clock-names = "spi", "wrap";
+               };
+
                sysirq: interrupt-controller@10200030 {
                        compatible = "mediatek,mt8135-sysirq",
                                     "mediatek,mt6577-sysirq";
@@ -143,6 +177,12 @@
                        reg = <0 0x10200030 0 0x1c>;
                };
 
+               apmixedsys: apmixedsys@10209000 {
+                       compatible = "mediatek,mt8135-apmixedsys";
+                       reg = <0 0x10209000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
                syscfg_pctl_b: syscfg_pctl_b@1020c000 {
                        compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
                        reg = <0 0x1020c000 0 0x1000>;
@@ -163,7 +203,8 @@
                        compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
                        reg = <0 0x11006000 0 0x400>;
                        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
-                       clocks = <&uart_clk>;
+                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+                       clock-names = "baud", "bus";
                        status = "disabled";
                };
 
@@ -171,7 +212,8 @@
                        compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
                        reg = <0 0x11007000 0 0x400>;
                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
-                       clocks = <&uart_clk>;
+                       clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+                       clock-names = "baud", "bus";
                        status = "disabled";
                };
 
@@ -179,7 +221,8 @@
                        compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
                        reg = <0 0x11008000 0 0x400>;
                        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
-                       clocks = <&uart_clk>;
+                       clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+                       clock-names = "baud", "bus";
                        status = "disabled";
                };
 
@@ -187,7 +230,8 @@
                        compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
                        reg = <0 0x11009000 0 0x400>;
                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
-                       clocks = <&uart_clk>;
+                       clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+                       clock-names = "baud", "bus";
                        status = "disabled";
                };