ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI

[karo-tx-linux.git] / arch / arm / boot / dts / sun7i-a20.dtsi

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 119f066f0d98aa16221855e04e8a3f83e4afe33e..dd567eac3dee99982b7b65cc43feeb3fca0aecc0 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -18,6 +18,14 @@
 
        aliases {
                ethernet0 = &emac;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+               serial4 = &uart4;
+               serial5 = &uart5;
+               serial6 = &uart6;
+               serial7 = &uart7;
        };
 
        cpus {
@@ -46,11 +54,12 @@
                #size-cells = <1>;
                ranges;
 
-               osc24M: osc24M@01c20050 {
+               osc24M: clk@01c20050 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
+                       clock-output-names = "osc24M";
                };
 
                osc32k: clk@0 {
@@ -60,21 +69,23 @@
                        clock-output-names = "osc32k";
                };
 
-               pll1: pll1@01c20000 {
+               pll1: clk@01c20000 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
+                       clock-output-names = "pll1";
                };
 
-               pll4: pll4@01c20018 {
+               pll4: clk@01c20018 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
+                       clock-output-names = "pll4";
                };
 
-               pll5: pll5@01c20020 {
+               pll5: clk@01c20020 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun4i-pll5-clk";
                        reg = <0x01c20020 0x4>;
@@ -82,7 +93,7 @@
                        clock-output-names = "pll5_ddr", "pll5_other";
                };
 
-               pll6: pll6@01c20028 {
+               pll6: clk@01c20028 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun4i-pll6-clk";
                        reg = <0x01c20028 0x4>;
@@ -95,6 +106,7 @@
                        compatible = "allwinner,sun4i-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
+                       clock-output-names = "cpu";
                };
 
                axi: axi@01c20054 {
@@ -102,6 +114,7 @@
                        compatible = "allwinner,sun4i-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
+                       clock-output-names = "axi";
                };
 
                ahb: ahb@01c20054 {
@@ -109,9 +122,10 @@
                        compatible = "allwinner,sun4i-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
+                       clock-output-names = "ahb";
                };
 
-               ahb_gates: ahb_gates@01c20060 {
+               ahb_gates: clk@01c20060 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun7i-a20-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
@@ -136,9 +150,10 @@
                        compatible = "allwinner,sun4i-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
+                       clock-output-names = "apb0";
                };
 
-               apb0_gates: apb0_gates@01c20068 {
+               apb0_gates: clk@01c20068 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun7i-a20-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
@@ -154,6 +169,7 @@
                        compatible = "allwinner,sun4i-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                       clock-output-names = "apb1_mux";
                };
 
                apb1: apb1@01c20058 {
@@ -161,9 +177,10 @@
                        compatible = "allwinner,sun4i-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
+                       clock-output-names = "apb1";
                };
 
-               apb1_gates: apb1_gates@01c2006c {
+               apb1_gates: clk@01c2006c {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun7i-a20-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
@@ -304,6 +321,34 @@
                        clock-output-names = "mbus";
                };
 
+               /*
+                * The following two are dummy clocks, placeholders used in the gmac_tx
+                * clock. The gmac driver will choose one parent depending on the PHY
+                * interface mode, using clk_set_rate auto-reparenting.
+                * The actual TX clock rate is not controlled by the gmac_tx clock.
+                */
+               mii_phy_tx_clk: clk@2 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <25000000>;
+                       clock-output-names = "mii_phy_tx";
+               };
+
+               gmac_int_tx_clk: clk@3 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <125000000>;
+                       clock-output-names = "gmac_int_tx";
+               };
+
+               gmac_tx_clk: clk@01c20164 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun7i-a20-gmac-clk";
+                       reg = <0x01c20164 0x4>;
+                       clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+                       clock-output-names = "gmac_tx";
+               };
+
                /*
                 * Dummy clock used by output clocks
                 */
@@ -373,6 +418,13 @@
                                allwinner,pull = <0>;
                        };
 
+                       uart2_pins_a: uart2@0 {
+                               allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+                               allwinner,function = "uart2";
+                               allwinner,drive = <0>;
+                               allwinner,pull = <0>;
+                       };
+
                        uart6_pins_a: uart6@0 {
                                allwinner,pins = "PI12", "PI13";
                                allwinner,function = "uart6";