arm: dts: tx6: remove obsolete regulator-boot-on properties

[karo-tx-linux.git] / arch / arm / boot / dts / tegra30.dtsi

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index d8783f0fae6354bd13a7939a7821d15bb830d054..2bd55cfd88adcb4d3e525ae45ea471a6376a8e34 100644 (file)
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -16,6 +16,76 @@
                serial4 = &uarte;
        };
 
+       pcie-controller {
+               compatible = "nvidia,tegra30-pcie";
+               device_type = "pci";
+               reg = <0x00003000 0x00000800   /* PADS registers */
+                      0x00003800 0x00000200   /* AFI registers */
+                      0x10000000 0x10000000>; /* configuration space */
+               reg-names = "pads", "afi", "cs";
+               interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
+                             GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+               interrupt-names = "intr", "msi";
+
+               bus-range = <0x00 0xff>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+
+               ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
+                         0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
+                         0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
+                         0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
+                         0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
+                         0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
+
+               clocks = <&tegra_car TEGRA30_CLK_PCIE>,
+                        <&tegra_car TEGRA30_CLK_AFI>,
+                        <&tegra_car TEGRA30_CLK_PCIEX>,
+                        <&tegra_car TEGRA30_CLK_PLL_E>,
+                        <&tegra_car TEGRA30_CLK_CML0>;
+               clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+               status = "disabled";
+
+               pci@1,0 {
+                       device_type = "pci";
+                       assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
+                       reg = <0x000800 0 0 0 0>;
+                       status = "disabled";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       nvidia,num-lanes = <2>;
+               };
+
+               pci@2,0 {
+                       device_type = "pci";
+                       assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
+                       reg = <0x001000 0 0 0 0>;
+                       status = "disabled";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       nvidia,num-lanes = <2>;
+               };
+
+               pci@3,0 {
+                       device_type = "pci";
+                       assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
+                       reg = <0x001800 0 0 0 0>;
+                       status = "disabled";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       nvidia,num-lanes = <2>;
+               };
+       };
+
        host1x {
                compatible = "nvidia,tegra30-host1x", "simple-bus";
                reg = <0x50000000 0x00024000>;
@@ -66,12 +136,13 @@
                gr3d {
                        compatible = "nvidia,tegra30-gr3d";
                        reg = <0x54180000 0x00040000>;
-                       clocks = <&tegra_car 24 &tegra_car 98>;
+                       clocks = <&tegra_car TEGRA30_CLK_GR3D
+                                 &tegra_car TEGRA30_CLK_GR3D2>;
                        clock-names = "3d", "3d2";
                };
 
                dc@54200000 {
-                       compatible = "nvidia,tegra30-dc";
+                       compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
                        reg = <0x54200000 0x00040000>;
                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA30_CLK_DISP1>,
@@ -561,6 +632,92 @@
                status = "disabled";
        };
 
+       usb@7d000000 {
+               compatible = "nvidia,tegra30-ehci", "usb-ehci";
+               reg = <0x7d000000 0x4000>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               phy_type = "utmi";
+               clocks = <&tegra_car TEGRA30_CLK_USBD>;
+               nvidia,needs-double-reset;
+               nvidia,phy = <&phy1>;
+               status = "disabled";
+       };
+
+       phy1: usb-phy@7d000000 {
+               compatible = "nvidia,tegra30-usb-phy";
+               reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
+               phy_type = "utmi";
+               clocks = <&tegra_car TEGRA30_CLK_USBD>,
+                        <&tegra_car TEGRA30_CLK_PLL_U>,
+                        <&tegra_car TEGRA30_CLK_USBD>;
+               clock-names = "reg", "pll_u", "utmi-pads";
+               nvidia,hssync-start-delay = <9>;
+               nvidia,idle-wait-delay = <17>;
+               nvidia,elastic-limit = <16>;
+               nvidia,term-range-adj = <6>;
+               nvidia,xcvr-setup = <51>;
+               nvidia.xcvr-setup-use-fuses;
+               nvidia,xcvr-lsfslew = <1>;
+               nvidia,xcvr-lsrslew = <1>;
+               nvidia,xcvr-hsslew = <32>;
+               nvidia,hssquelch-level = <2>;
+               nvidia,hsdiscon-level = <5>;
+               status = "disabled";
+       };
+
+       usb@7d004000 {
+               compatible = "nvidia,tegra30-ehci", "usb-ehci";
+               reg = <0x7d004000 0x4000>;
+               interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+               phy_type = "ulpi";
+               clocks = <&tegra_car TEGRA30_CLK_USB2>;
+               nvidia,phy = <&phy2>;
+               status = "disabled";
+       };
+
+       phy2: usb-phy@7d004000 {
+               compatible = "nvidia,tegra30-usb-phy";
+               reg = <0x7d004000 0x4000>;
+               phy_type = "ulpi";
+               clocks = <&tegra_car TEGRA30_CLK_USB2>,
+                        <&tegra_car TEGRA30_CLK_PLL_U>,
+                        <&tegra_car TEGRA30_CLK_CDEV2>;
+               clock-names = "reg", "pll_u", "ulpi-link";
+               status = "disabled";
+       };
+
+       usb@7d008000 {
+               compatible = "nvidia,tegra30-ehci", "usb-ehci";
+               reg = <0x7d008000 0x4000>;
+               interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+               phy_type = "utmi";
+               clocks = <&tegra_car TEGRA30_CLK_USB3>;
+               nvidia,phy = <&phy3>;
+               status = "disabled";
+       };
+
+       phy3: usb-phy@7d008000 {
+               compatible = "nvidia,tegra30-usb-phy";
+               reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
+               phy_type = "utmi";
+               clocks = <&tegra_car TEGRA30_CLK_USB3>,
+                        <&tegra_car TEGRA30_CLK_PLL_U>,
+                        <&tegra_car TEGRA30_CLK_USBD>;
+               clock-names = "reg", "pll_u", "utmi-pads";
+               nvidia,hssync-start-delay = <0>;
+               nvidia,idle-wait-delay = <17>;
+               nvidia,elastic-limit = <16>;
+               nvidia,term-range-adj = <6>;
+               nvidia,xcvr-setup = <51>;
+               nvidia.xcvr-setup-use-fuses;
+               nvidia,xcvr-lsfslew = <2>;
+               nvidia,xcvr-lsrslew = <2>;
+               nvidia,xcvr-hsslew = <32>;
+               nvidia,hssquelch-level = <2>;
+               nvidia,hsdiscon-level = <5>;
+               status = "disabled";
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;