Add GPL-2.0+ SPDX-License-Identifier to source files

[karo-tx-uboot.git] / arch / arm / cpu / arm920t / s3c24x0 / speed.c

diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c
index b13283a798e884ec141d846278966ea69077c395..3701c5d9a3da6aca57b50c9bac3b652248cec727 100644 (file)
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c
@@ -5,23 +5,7 @@
  * (C) Copyright 2002
  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* This code should work for both the S3C2400 and the S3C2410
@@ -54,9 +38,9 @@ static ulong get_PLLCLK(int pllreg)
        ulong r, m, p, s;
 
        if (pllreg == MPLL)
-               r = readl(&clk_power->MPLLCON);
+               r = readl(&clk_power->mpllcon);
        else if (pllreg == UPLL)
-               r = readl(&clk_power->UPLLCON);
+               r = readl(&clk_power->upllcon);
        else
                hang();
 
@@ -64,7 +48,12 @@ static ulong get_PLLCLK(int pllreg)
        p = ((r & 0x003F0) >> 4) + 2;
        s = r & 0x3;
 
+#if defined(CONFIG_S3C2440)
+       if (pllreg == MPLL)
+               return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
+#endif
        return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+
 }
 
 /* return FCLK frequency */
@@ -77,8 +66,23 @@ ulong get_FCLK(void)
 ulong get_HCLK(void)
 {
        struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-       return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+#ifdef CONFIG_S3C2440
+       switch (readl(&clk_power->clkdivn) & 0x6) {
+       default:
+       case 0:
+               return get_FCLK();
+       case 2:
+               return get_FCLK() / 2;
+       case 4:
+               return (readl(&clk_power->camdivn) & (1 << 9)) ?
+                       get_FCLK() / 8 : get_FCLK() / 4;
+       case 6:
+               return (readl(&clk_power->camdivn) & (1 << 8)) ?
+                       get_FCLK() / 6 : get_FCLK() / 3;
+       }
+#else
+       return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
+#endif
 }
 
 /* return PCLK frequency */
@@ -86,7 +90,7 @@ ulong get_PCLK(void)
 {
        struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 
-       return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
+       return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
 }
 
 /* return UCLK frequency */