* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
{
}
+#ifdef CONFIG_MX28
static void initialize_dram_values(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+#else
+static void initialize_dram_values(void)
+{
+ int i;
+
+ mxs_adjust_memory_params(dram_vals);
+
+ /*
+ * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+ * per FSL bootlets code.
+ *
+ * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+ * "reserved".
+ * HW_DRAM_CTL8 is setup as the last element.
+ * So skip the initialization of these HW_DRAM_CTL registers.
+ */
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+ if (i == 8 || i == 27 || i == 28 || i == 35)
+ continue;
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ }
-#ifdef CONFIG_MX23
/*
* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
* element to be set
*/
writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
-#endif
}
+#endif
static void mxs_mem_init_clock(void)
{
writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
- early_delay(11000);
/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
&clkctrl_regs->hw_clkctrl_emi);
+ while (readl(&clkctrl_regs->hw_clkctrl_emi) & CLKCTRL_EMI_BUSY_REF_EMI)
+ ;
/* Unbypass EMI */
writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
-
- early_delay(10000);
}
static void mxs_mem_setup_cpu_and_hbus(void)
&clkctrl_regs->hw_clkctrl_clkseq_set);
/* HBUS = 151MHz */
- writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
- writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
- &clkctrl_regs->hw_clkctrl_hbus_clr);
-
- early_delay(10000);
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_hbus,
+ CLKCTRL_HBUS_DIV_MASK,
+ 3 << CLKCTRL_HBUS_DIV_OFFSET);
+ while (readl(&clkctrl_regs->hw_clkctrl_hbus) & CLKCTRL_HBUS_ASM_BUSY)
+ ;
/* CPU clock divider = 1 */
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
- CLKCTRL_CPU_DIV_CPU_MASK, 1);
+ CLKCTRL_CPU_DIV_CPU_MASK,
+ 1 << CLKCTRL_CPU_DIV_CPU_OFFSET);
+ while (readl(&clkctrl_regs->hw_clkctrl_cpu) & CLKCTRL_CPU_BUSY_REF_CPU)
+ ;
/* Disable CPU bypass */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
-
- early_delay(15000);
}
-static void mxs_mem_setup_vdda(void)
-{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+#define MEM_ABORT_FUNC
- writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
- (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
- POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
- &power_regs->hw_power_vddactrl);
+#ifdef MEM_ABORT_FUNC
+static void data_abort_memdetect_handler(void)
+{
+ asm volatile("subs pc, lr, #4");
}
+#endif
uint32_t mxs_mem_get_size(void)
{
uint32_t sz, da;
uint32_t *vt = (uint32_t *)0x20;
- /* The following is "subs pc, r14, #4", used as return from DABT. */
- const uint32_t data_abort_memdetect_handler = 0xe25ef004;
/* Replace the DABT handler. */
da = vt[4];
- vt[4] = data_abort_memdetect_handler;
-
- sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+#ifdef MEM_ABORT_FUNC
+ vt[4] = (uint32_t)data_abort_memdetect_handler;
+#else
+ vt[4] = (uint32_t)&&data_abort_memdetect_handler;
+#endif
+ sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE * 2);
/* Restore the old DABT handler. */
vt[4] = da;
return sz;
+
+#ifndef MEM_ABORT_FUNC
+data_abort_memdetect_handler:
+ asm volatile("subs pc, lr, #4");
+#endif
}
#ifdef CONFIG_MX23
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
- writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
- POWER_VDDMEMCTRL_ENABLE_ILIMIT |
- POWER_VDDMEMCTRL_ENABLE_LINREG |
- POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
- &power_regs->hw_power_vddmemctrl);
-
- early_delay(10000);
+ clrbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_ILIMIT);
- writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
- POWER_VDDMEMCTRL_ENABLE_LINREG,
- &power_regs->hw_power_vddmemctrl);
}
static void mx23_mem_init(void)
initialize_dram_values();
- /* Set START bit in DRAM_CTL16 */
+ /* Set START bit in DRAM_CTL8 */
setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
early_delay(20000);
/* Adjust EMI port priority. */
- clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
early_delay(20000);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
- /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
- while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
- ;
}
#endif
mxs_mem_init_clock();
- mxs_mem_setup_vdda();
-
#if defined(CONFIG_MX23)
mx23_mem_init();
#elif defined(CONFIG_MX28)
mx28_mem_init();
#endif
- early_delay(10000);
-
mxs_mem_setup_cpu_and_hbus();
}
projects / karo-tx-uboot.git / blobdiff