*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+ static int trg __attribute__((section(".data")));
+
+ switch (trg) {
+ case 0:
+ case 1:
+ if (readl(&wdtimer->wdtwwps) & (1 << 4))
+ return;
+ writel(trg ? 0x5555 : 0xaaaa, &wdtimer->wdtwspr);
+ break;
+ case 2:
+ if (readl(&wdtimer->wdtwwps) & (1 << 2))
+ return;
+ /* 10 sec timeout */
+ writel(-32768 * 10, &wdtimer->wdtwldr);
+
+ if (readl(&wdtimer->wdtwwps) & (1 << 0))
+ return;
+ /* prescaler = 1 */
+ writel(0, &wdtimer->wdtwclr);
+ break;
+
+ case 3:
+ case 4:
+ /* enable watchdog */
+ if (readl(&wdtimer->wdtwwps) & (1 << 4))
+ return;
+ writel((trg & 1) ? 0xBBBB : 0x4444, &wdtimer->wdtwspr);
+ break;
+
+ default:
+ /* retrigger watchdog */
+ if (readl(&wdtimer->wdtwwps) & (1 << 3))
+ return;
+
+ writel(trg, &wdtimer->wdtwtgr);
+ trg ^= 0x2;
+ return;
+ }
+ trg++;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int cpu_mmc_init(bd_t *bis)
+int __cpu_mmc_init(bd_t *bis)
{
int ret;
- ret = omap_mmc_init(0, 0, 0);
+ ret = omap_mmc_init(0, 0, 0, -1, -1);
if (ret)
return ret;
- return omap_mmc_init(1, 0, 0);
+ return omap_mmc_init(1, 0, 0, -1, -1);
}
+/* let platform code be able to override this! */
+int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__cpu_mmc_init")));
#endif
void setup_clocks_for_console(void)
{
#ifdef CONFIG_AM335X_USB0
musb_register(&otg0_plat, &otg0_board_data,
- (void *)AM335X_USB0_OTG_BASE);
+ (void *)USB0_OTG_BASE);
#endif
#ifdef CONFIG_AM335X_USB1
musb_register(&otg1_plat, &otg1_board_data,
- (void *)AM335X_USB1_OTG_BASE);
+ (void *)USB1_OTG_BASE);
#endif
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+void rtc32k_enable(void)
+{
+ struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+ /*
+ * Unlock the RTC's registers. For more details please see the
+ * RTC_SS section of the TRM. In order to unlock we need to
+ * write these specific values (keys) in this order.
+ */
+ writel(0x83e70b13, &rtc->kick0r);
+ writel(0x95a4f1e0, &rtc->kick1r);
+
+ /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+ writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+void uart_soft_reset(void)
+{
+ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ u32 regval;
+
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_RESET;
+ writel(regval, &uart_base->uartsyscfg);
+ while ((readl(&uart_base->uartsyssts) &
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_SMART_IDLE_EN;
+ writel(regval, &uart_base->uartsyscfg);
+}
+#endif